Six Companies from the RISC-V Ecosystem to Host Speaking Sessions at Conference
(BUSINESS WIRE) — October 3, 2017 — RISC-V Foundation:
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WHERE: |
The 15th International System-on-Chip (SoC) Conference, Exhibit & Workshops, University of California, Irvine (UCI) , Irvine, Calif., 92697, Calit2 Building 2 | |
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WHEN: |
Wednesday, Oct. 18 to Thursday, Oct. 19, 2017 | |
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WHAT: |
The RISC-V Foundation will feature six member organizations at this year’s International SoC Conference. Ted Speers, VP and Head of Product Architecture and Planning for Microsemi SoC Group, a founding RISC-V member, is a keynote speaker addressing the challenges and possibilities of the open, free RISC-V ISA. Additionally, Foundation members including Codasip, Dover Microsystems, Imperas, SiFive and UltraSoC will present at this year’s show. RISC-V speaking sessions include: |
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Keynote: “RISC-V Challenges and Possibilities
- When: Wednesday, Oct. 18, 2017 at 1 – 1:50 p.m. PT
- Who: Ted Speers at Microsemi
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Introducing the New RISC-V U54 Coreplex
- When: Wednesday, Oct. 18, 2017 at 1:50 – 2:20 p.m. PT
- Who: Jack Kang at SiFive
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RISC-V Models and Simulation Enable Early Software Bring Up
- When: Wednesday, Oct. 18, 2017 at 2:20 – 2:50 p.m. PT
- Who: Larry Lapides at Imperas Software Ltd.
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System-wide Visibility and Analytics
- When: Wednesday, Oct. 18, 2017 at 2:50 – 3:20 p.m. PT
- Who: Gajinder Panesar at UltraSoC
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The Dover PIPE: Processor Interlocks for Policy Enforcement
- When: Wednesday, Oct. 18, 2017 at 3:30 – 4 p.m. PT
- Who: Steven Milburn at Dover Microsystems
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A High-Level Design Methodology for RISC-V Processor Development
- When: Wednesday, Oct. 18, 2017 at 4 – 4:30 p.m. PT
- Who: Dan Ganousis at Codasip
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RISC-V and prpl: Why RISC-V will Become the Most Secure Processor
Architecture
- When: Thursday, Oct. 19, 2017 at 4 – 4:30 p.m. PT
- Who: Art Swift at prpl Foundation
