The SiP Flow help designers ensure component design success with accurate and systematic analysis of inter-die and package effects

Hsinchu, Taiwan — July 28, 2009 — Global Unichip Corp. (GUC; TW: 3443), the world's leading Design Foundry service provider, announced today the application and validation of System-in-Package (SiP) design solution in TSMC Reference Flow 10.0 as the fruit of collaboration with TSMC. The SiP methodology has been fully qualified with GUC production case and achieved good silicon correlation.

The SiP Flow provides die-to-package co-design with comprehensive SiP design analysis such as component timing, IR drop, signal-integrity/simultaneous switching noise, and thermal analysis. The SiP flow also offers die-to-package DRC/LVS verification solutions and electrical, physical design guideline. The SiP timing has been correlated to silicon data with high accuracy.

"TSMC Reference Flow 10.0 enables designers to effectively use package design capability to deliver a more competitive component." said ST Juang, Senior Director of Design Infrastructure Marketing at TSMC. "The integrated design approach reduces extra design margins used in modeling package effects, so customers can design their SiPs more systematically and ensure first time success for their product."

Jim Lai, president and COO of GUC also said, "We offer customers more design analysis and capability that include multiple die and package effects. This joint effort between TSMC and GUC also demonstrates our design leadership and differentiation from competitor's solution by showing robust SiP design capability, ensuring component success, not just die success."

TSMC and GUC have been collaborating to provide the best and most advanced design solution to our end customers, in both SoC and SiP. This TSMC Reference Flow 10.0 SiP flow offers a complete end-to-end solution to extend the service from SoC to SiP. It not only creates customer value but also provides a lowest risk path for customer's next project.