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DVCon U.S. 2024 Announces Stuart Sutherland Best Paper & Best Poster Winners & Conference Highlights

GAINESVILLE, Fla., March 19, 2024 (GLOBE NEWSWIRE) -- The 2024 Design and Verification Conference and Exhibition U.S. (DVCon U.S.), sponsored by Accellera Systems Initiative (Accellera), concluded its 36th annual event in San Jose, CA earlier this month. The 2024 Best Paper and Poster winners, as voted on by attendees, were announced during a reception in the exhibit hall on March 6.

Participants came from 28 countries and represented approximately 327 companies, with 394 attending the conference and exhibition for the first time. Overall attendance for DVCon U.S. 2024 was approximately 975, including attendees from 25 exhibiting companies.

“It was really an exciting time to be back at DVCon U.S.,” stated Tom Fitzpatrick, DVCon U.S. 2024 General Chair. "The camaraderie among industry peers created a lot of energy and interaction during the sessions and exhibition. We had many sessions that were standing room only. Artificial intelligence’s influence permeated presentations and discussions, underscoring DVCon’s commitment to empowering practicing engineers looking for ways to improve their day-to-day projects, as well as a look toward what will be impactful in the future.”

The award for the Stuart Sutherland Best Paper Presentation, as voted by conference attendees, went to Aman Kumar, Deepak Narayan Gadde, Thomas Nalapat, Evgenii Rezunov, and Fabio Cappellini, Infineon Technologies for their paper, “All Artificial, Less Intelligence: GenAI through the Lens of Formal Verification.” Second place was awarded to Neha Goyal and Justin Refice, Nvidia Corp. for “Leveraging Interface Classes to Improve UVM TLM.” William Moore, Paradigm Works took third place for his paper, “Gherkin Implementation in SystemVerilog Brings Agile Behavior-Driven Development to UVM.”

Top honors for best poster went to Sharada Vajja, Raghu Alamuri, Saksham Mehra, Google LLC for “AI-based Algorithms to Analyze and Optimize Performance Verification Efforts.” Nimay Shah, Pranav Dhayagude, and Paul Wright, Analog Devices Inc., and Raj Mitra, Cadence Design Systems, took second place for “Enabling True System-Level, Mixed-Signal Emulation.” Third place was awarded to Santosh Kumar, Yogish Raja, Geetika Agrawal, Karthikeyan SugumaranArjun Vazhayil, and Tommy Brunansky, Qualcomm Technologies Inc. for their poster “Scalable Functional Verification using Portable Stimulus Standard.”

Highlights of the Week: 

Save the date:  DVCon U.S. 2025 will be held February 24-27 at the DoubleTree Hotel in San Jose, California. Tom Fitzpatrick will continue as General Chair for DVCon U.S. 2025.

About DVCon
DVCon is the premier conference for discussion of the functional design and verification of electronic systems. DVCon is sponsored by Accellera Systems Initiative, an independent, not-for-profit organization dedicated to creating design and verification standards required by systems, semiconductor, intellectual property (IP) and electronic design automation (EDA) companies. For more information about Accellera, please visit www.accellera.org. For more information about DVCon U.S., please visit here. Follow DVCon on Facebook, LinkedIn or @dvcon_us on Twitter or to comment, please use #dvcon_us.

For more information, please contact:
Laura LeBlanc                                         
Conference Catalysts, LLC                              
352-872-5544 Ext. 115                              
lleblanc@conferencecatalysts.com                     

Barbara Benjamin
HighPointe Communications
503-209-2323
barbara@hipcom.com 


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