This chapter dealt with system level aspects where a D/A interface with Sinc approximated semidigital reconstruction filter as an example of a system where accuracy and noise give constraints on the total power consumption. It shows that low-power techniques at the highest level of abstraction can lead to power savings which cannot be obtained unless the complete system is taken into study.

The method used in this chapter is based on a new approach, the Sinc approximation approach, either in frequency domain or in time domain. A differential, current-driven 16-bit D/A interface with Sinc approximated semidigital reconstruction filter has been presented. The benefit of the differential approach is the reduction of substrate interferences and the increase in voltage swing necessary to have large dynamic range.

The chapter focusses on the optimization of the number of coefficients of the FIR filter. An FIR filter with a large number of coefficients needs a large number of additional digital circuitry increasing the area, power consumption and complicating more the clock distribution. A large number of coefficients, requires more shift registers and therefore, the power in digital domain will increase. The overhead in power due to clock distribution has to be added. The accuracy of the coefficients is subject to process tolerance caused by rounding of the small coefficients and quantization to the process grid span. A large number of coefficients implies big differences between coefficients. The accuracy of the smaller coefficients is impaired with consequences on the stop-band rejection of the filter.

By using Sinc approximation in the frequency domain and an iterative procedure one can reduce the number of coefficients taking into account process tolerances such that the out of band rejection of noise requirement is met. Compared to the standard solutions we have reduced about four times the number of the coefficients for the same requirements. With only 25 coefficients we get more than 50dB stopband rejection of the out of band noise. The resolution of the system is impaired by circuit nonidealities such as component noise, mismatches, device nonlinearities, substrate bounce and clock jitter. Some of those issues have been treated here and an analysis of the matching, noise and clock jitter is provided.

To increase the matching in the differential FIR filter, a floating mirror has been used. The differential opamp with common-mode control can be chopped or unchopped depending on the resolution required. The D/A interface has been realized on chip in a 0.8mm CMOS, 5V technology and the measurement results have been presented.

Another approach is the Sinc approximation method in the time domain. By using this method the best partitioning of the system in terms of power can be found. Accordingly, power consumption in the digital domain can be reduced. The price paid is an increase of the filter complexity with the benefit of keeping the same power consumption in the analog part. The principle of the method is discussed and an example is given.