Collaborating on Two Demonstrations of 25G SerDes at DesignCon;
Compliance
Benefits Push toward 100G Ethernet Infrastructure
SAN JOSE, Calif. & SINGAPORE — (BUSINESS WIRE) — January 30, 2012 — Avago Technologies (Nasdaq: AVGO), a leading supplier of analog interface components for communications, industrial and consumer applications, today announced that its 25-Gbps Serializer/Deserializer (SerDes) core in 28-nm process technology has demonstrated compliance with the Common Electrical Interface (CEI) standard for 25G Long Reach (LR). Achieving CEI-25G-LR compliance eases design of data networking applications and aligns with the push for 100G Ethernet Infrastructure to extend cloud computing, multimedia and virtualization capabilities.
Avago also announced it will demonstrate its 25G SerDes cores in backplane applications at the DesignCon 2012 exhibition in the Santa Clara Convention Center in Santa Clara, California from January 31 to February 1. The embedded SerDes cores are often integrated in Application-Specific Integrated Circuits (ASICs) used for data communication in networking, computing and storage applications. The demonstrations, which show the Avago 25G SerDes running on over 30-inch PC board traces, will take place in the TE Connectivity booth (#411) and in the Amphenol TCS booth (#501).
“This compliance is not only another first for our SerDes cores, but it marks a significant step forward in the march to 100G Ethernet Infrastructure,” said Frank Ostojic, vice president and general manager of the ASIC Products Division at Avago. “As part of the push toward 100G, Avago is planning to use our 25G SerDes as the basis for future standard products. Capable of driving 5 meters of copper cabling at low power, the 25G SerDes is suitable for a range of applications and is now available to a larger group of customers.”
Avago Intellectual Property (IP) SerDes cores can be easily integrated due to their modular, multirate architecture, and Avago has integrated over 400 SerDes channels on a single ASIC. The 28-nm Avago SerDes cores feature a unique decision feedback equalization (DFE) architecture, resulting in a number of key performance differentiators such as low overall power, best-in-class data latency, and best-in-class jitter and crosstalk tolerance.
Avago has an established history of delivering on-time, reliable, high-performance ASICs. Three decades of design experience, state-of-the art hierarchical design methodology, and an IP portfolio covering multiple standards form the company’s foundation for supplying complex ASICs to the wired communications market. The broad Avago SerDes portfolio supports a wide range of standards such as PCI Express, Fibre Channel, XAUI, CEI, 10GBASE-KR and SFI, providing the flexibility to address optical, copper and backplane applications.
About Avago Technologies
Avago Technologies is a leading supplier of analog interface components for communications, industrial and consumer applications. By leveraging its core competencies in III-V compound and silicon semiconductor design and processing, the company provides an extensive range of analog, mixed signal and optoelectronics components and subsystems to approximately 40,000 end customers. Backed by strong customer service support, the company's products serve four diverse end markets: wireless communications, wired infrastructure, industrial and automotive electronics, and consumer and computing peripherals. Avago has a global employee presence and heritage of technical innovation dating back 50 years to its Hewlett-Packard roots. Information about Avago is available on the Web at www.avagotech.com.
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