SMIC Offers a Full Set of ESD Protection Service to Enhance the Whole Chip ESD Design for Customers

SHANGHAI, March 25, 2014 -- Semiconductor Manufacturing International Corporation ("SMIC",NYSE: SMI; SEHK: 981), China's largest and most advanced semiconductor foundry, announced today that a full set of Electrostatic Discharge (ESD) protection service, including documents, checklists, PERC Suite, floor plan review, and risk management services, has been offered to IC design customers to enhance the whole chip ESD design and ensure their first silicon success.

Along with the rapid progress of semiconductor manufacturing process technologies, ESD has become a more serious and challenging problem when the dimension of device shrinks to sub-65nm. Just depending on I/O design is not sufficient for ESD protection design, especially in the interface of different power domain circuits. The designers become more concerned about the ESD problem since the gate oxide becomes more easily damaged as the dimension are reduced. Therefore, the conception of whole chip ESD design should be recognized.

In order to help customers to manage ESD risk and implement the whole chip ESD design, SMIC provides 3 lines of defense designated on ESD protection: first, SMIC offers a whole set of documents and checklists which customers must follow during design stage to plan their chip level ESD protection in different process technologies at SMIC. Second, a newly developed Mentor PERC Suite is provided for ESD protection automatic check at chip level when taped out. Last but not least, SMIC provides ESD floor plan review and risk management services upon customers' requests. The floor plan review covers the IO application, placement/route and final GDS review for the customer who uses SMIC's IO library. All the solutions are aimed to improve chip's ESD protection performance.

"Nowadays, good ESD protection is the result of collaborative effort from robust I/O design service by the foundry, full chip level ESD protection scheme by customers and conscientious IP level ESD protection by third party providers," said Dr. Tianshen Tang, senior vice president of SMIC's Design Service Center. "At SMIC, we thoroughly investigate to ensure customers' ease of access to all SMIC ESD protection solutions. Several years ago, SMIC had taken the lead in carrying out the comprehensive ESD research in the industry, and not only solved the technical problems with experts and suppliers, but also explored and practiced the ESD protection design and test processes as well as business model with important clients. We accumulated a lot of successful experiences. In 2013, the pass rate of ESD floor plan review cases by SMIC exceeded 95%. Based on the successful trial operation, SMIC officially announces the launch of overall ESD protection design services. It symbolizes our service abilities for IC design customers have become more professional, standardized, advanced and comprehensive."

About SMIC
Semiconductor Manufacturing International Corporation ("SMIC"; NYSE: SMI; SEHK: 981) is one of the leading semiconductor foundries in the world and the largest and most advanced foundry in mainland China. SMIC provides integrated circuit (IC) foundry and technology services at 0.35-micron to 40-nanometer and has begun offering advanced 28nm process technology. Headquartered in Shanghai, China, SMIC has a 300mm wafer fabrication facility (fab) and a 200mm mega-fab in Shanghai, a 300mm mega-fab in Beijing, a 200mm fab in Tianjin, and a 200mm fab project under development in Shenzhen. SMIC also has customer service and marketing offices in the U.S., Europe, Japan, and Taiwan, and a representative office in Hong Kong. For more information, please visit www.smics.com.

Safe Harbor Statements
(Under the Private Securities Litigation Reform Act of 1995)

This document contains, in addition to historical information, "forward-looking statements" within the meaning of the "safe harbor" provisions of the U.S. Private Securities Litigation Reform Act of 1995. These forward-looking statements are based on SMIC's current assumptions, expectations and projections about future events. SMIC uses words like "believe," "anticipate," "intend," "estimate," "expect," "project" and similar expressions to identify forward looking statements, although not all forward-looking statements contain these words. These forward-looking statements are necessarily estimates reflecting the best judgment of SMIC's senior management and involve significant risks, both known and unknown, uncertainties and other factors that may cause SMIC's actual performance, financial condition or results of operations to be materially different from those suggested by the forward-looking statements including, among others, risks associated with cyclicality and market conditions in the semiconductor industry, intense competition, timely wafer acceptance by SMIC's customers, timely introduction of new technologies, SMIC's ability to ramp new products into volume, supply and demand for semiconductor foundry services, industry overcapacity, shortages in equipment, components and raw materials, availability of manufacturing capacity, financial stability in end markets and intensive intellectual property litigation in high tech industry.

In addition to the information contained in this document, you should also consider the information contained in our other filings with the SEC, including our annual report on Form 20-F filed with the SEC on April 15, 2013, as amended on December 19, 2013, especially in the "Risk Factors" section and such other documents that we may file with the SEC or SEHK from time to time, including on Form 6-K. Other unknown or unpredictable factors also could have material adverse effects on our future results, performance or achievements. In light of these risks, uncertainties, assumptions and factors, the forward-looking events discussed in this document may not occur. You are cautioned not to place undue reliance on these forward-looking statements, which speak only as of the date stated or, if no date is stated, as of the date of this document.



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