Wednesday, April 9, 2014
2:00 pm EDT / 11:00 am PDT
With the rapid development of IP and EDA tools, designing a mixed-signal chip can be quite easy. But how easy depends on selecting the appropriate technology partners to meet your chip needs. ARM® high-efficiency processors and optimized physical and system IP, coupled with the Cadence® Virtuoso® integration solution, enable customers to reduce time to market, realize power, performance, and area design targets, and satisfy ever-increasing competitive market demands.
Attend this one-hour webinar to learn about:
2:00 pm EDT / 11:00 am PDT
With the rapid development of IP and EDA tools, designing a mixed-signal chip can be quite easy. But how easy depends on selecting the appropriate technology partners to meet your chip needs. ARM® high-efficiency processors and optimized physical and system IP, coupled with the Cadence® Virtuoso® integration solution, enable customers to reduce time to market, realize power, performance, and area design targets, and satisfy ever-increasing competitive market demands.
Attend this one-hour webinar to learn about:
- Designing low-power mixed-signal SoCs
- ARM MCUs, physical IP, and Cadence mixed-signal design tools
- Analog, mixed-signal, and Internet of Things applications
