ARM Extends Scalability of CoreLink for Infrastructure Compute

CAMBRIDGE, England — (BUSINESS WIRE) — October 22, 2014 — ARM today announced new additions to its suite of enterprise-class ARM^® CoreLink^™ Cache Coherent Network (CCN) SoC interconnects, underscoring its commitment to providing a flexible architecture from sensors to servers. The CoreLink CCN-502 and CoreLink CCN-512 interconnects extend the current family for data center and infrastructure equipment that scales from the edge of the network to the core.

“Growth in mobile computing and the Internet of Things is connecting more devices and aggregating more data across the network, and that demands an increasingly flexible and efficient computing infrastructure,” said James McNiven, general manager, systems and software group, ARM. “Our new CoreLink CCN-502 and CoreLink CCN-512 interconnects build on a common architecture, scaling from high efficiency Power-over-Ethernet wireless access points, to high compute density 48-core solutions.”

Next generation infrastructure deployments require complex heterogeneous compute solutions that can address the demands of exponentially growing throughput demands without compromising on manageability and flexibility. The entire family of CoreLink CCN interconnects, including the CoreLink CCN-504 and CoreLink CCN-508, offer enterprise-class features such as RAS, ECC and advanced QoS to address a wide range of infrastructure SoCs ranging from 1 to 48-cores of CPU that can be coupled with a variety of heterogeneous compute elements. All CoreLink CCN interconnects include native ARM AMBA^® 5 CHI interfaces providing high frequency, non-blocking data transfers and an integrated Level 3 Cache and Snoop Filter.

Optimized for area and power in Small Cell Base Stations and Wireless Access Points

CoreLink CCN-502 is an area-optimized interconnect for up to four quad-core processor clusters, offering the most cost and power-efficient solution in the CoreLink CCN family. Applications may include small cell base stations and sub-10W Power-over-Ethernet wireless access points.

Key benefits and features of the CoreLink CCN-502 include:

70% area reduction over CoreLink CCN-504 at 1MB
Optional, integrated Level 3 System Cache configurable up to 8MB
High frequency, high performance interconnect supporting up to 0.8Tb/s sustained bandwidth
1 to 4 processor clusters including ARM Cortex^®-A53 and Cortex-A57 processors with AMBA 5 CHI
1 to 4 channels of DDR3/4 memory with DMC-520 supporting 72-bit ECC DIMMs
Up to 9 1/O coherent ports with AMBA 4 AX14/ACE-Lite interfaces in addition to CPU and DMC ports

Highest Compute Density for Macro Cell Base Stations, Core Networks and Servers

The CoreLink CCN-512 is the highest performance solution in the CoreLink CCN family and offers partners the ability to create dense, 48-core heterogeneous compute solutions with mix of CPUs, DSPs and accelerators and bandwidths up to 1.8 terabits per second.

Key benefits and features of the CoreLink CCN-512 include:

Compute Density of up to 12 CPU Clusters (48 cores) including Cortex-A53 and Cortex-A57 with AMBA 5 CHI
Integrated Level L3 System Cache up to 32MB
Highest performance CoreLink CCN interconnect supporting up to 1.8Tb/s sustained bandwidth
1 to 4 channels of DDR3/4 memory with DMC-520 supporting 72-bit ECC DIMMs
Up to 24 1/O coherent ports with AMBA 4 AX14/ACE-Lite interfaces in addition to CPU and DMC ports

More details on CoreLink CCN-502 and CoreLink CCN-512 can be found here.

Partner Support

To-date, ARM has licensed the enterprise-class CCN CoreLink technology to more than ten silicon partners including AMD, Avago and Freescale. In addition there is wide ecosystem support for AMBA 5 CHI including verification IP from Cadence, Mentor and Synopsys.

“In order to deliver high-bandwidth and scalable cache coherent interconnect across our ARM Cortex-A57 based SoCs, AMD is pleased to announce that we have licensed and integrated ARM CoreLink CCN interconnects into our upcoming AMD Opteron^™ A-Series SoC, codenamed ‘Seattle’ and the AMD Embedded R-Series SoC, codenamed ‘Hierofalcon,’” said Suresh Gopalakrishnan, corporate vice president and general manager, server business unit, AMD.

“As SoC designs continue to grow in size and complexity, functional verification becomes an increasingly critical component of the development cycle,” said Erik Panu, vice president, research and development, IP Group, Cadence. “The Cadence Verification IP solution for AMBA 5 CHI and JasperGold Intelligent Proof Kit for AMBA 5 CHI protocols are already helping ARM partners roll-out their next-generation designs incorporating the most advanced interconnect standards while speeding time to market.”

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