ALAMEDA, CA, May 28, 2015 -- Verific Design Automation, provider of SystemVerilog, VHDL and UPF parsers invites attendees of the 52nd Design Automation Conference (DAC) to stop by its booth (#2714) to pick up this year's giraffe giveaway and learn more about its SystemVerilog, Verilog, VHDL and UPF parser platforms. Verific's software is used by electronic design automation (EDA) companies, including 24 exhibiting at DAC, as the front end for their analysis, emulation, simulation, synthesis and verification tools.
WHEN: Monday, June 8, and Tuesday, June 9, from 10 a.m. until 7 p.m. and Wednesday, June 10, from 10 a.m. until 6 p.m.
WHERE: Moscone Center, San Francisco
More details about Verific can be found at: www.verific.com
Atrenta and Calypto, long-time Verific customers, sponsored the "I LOVE DAC" three-day exhibit program.
While it is no longer available, registration information can be found at:
www.dac.com
About Verific Design Automation
Verific Design Automation, with offices in Alameda, Calif., and Kolkata, India, provides parsers and elaborators for SystemVerilog, Verilog, VHDL and UPF. Verific's software is used worldwide by the EDA and semiconductor community in synthesis, simulation, formal verification, emulation, debugging, virtual prototyping, and design-for-test applications, which combined have shipped more than 60,000 copies. Corporate headquarters is located at: 1516 Oak Street, Suite 115, Alameda, Calif. 94501. Telephone: (510) 522-1555. Email: Email Contact Website: www.verific.com
Contacts:
Nanette Collins
Public Relations for Verific Design Automation
(617) 437-1822
Email Contact
Verific Design Automation acknowledges trademarks or registered trademarks of other organizations for their respective products and services.
