Austin, Texas, June 6, 2016 — Menta SAS, a provider of embedded FPGA (eFPGA) Intellectual Property (IP), today announced the next generation of its embedded programmable logic IP cores for SoCs. The programmable logic, available as both custom and pre-defined IP cores, is based on Menta’s proven eFPGA fabric, optimized to deliver the industry’s best combination of performance, reduced size and low power consumption.
The company has also expanded support to additional technology nodes. In addition to TSMC 28nm HPM and ST Microelectronics 28nm FDSOI, the IP is now optimized for GlobalFoundries 14nm LPP process. Menta’s eFPGA technology will be demonstrated at booth #640 from June 6-9, 2016 at the Design Automation Conference in Austin, Texas.
Programmability is essential feature of next-generation SoCs
Embedding an FPGA fabric as an IP core in a SOC allows semiconductor designers to update the silicon at will post production, thereby eliminating the cost and time associated with re-spinning silicon. These features are becoming critical to balance the sometimes conflicting requirements to preserve investment and get to market faster with the complex parallel and co-processing SoCs used in today’s automotive, aerospace, defense, industrial, computing and Internet of Things applications.
“Over three product generations, Menta’s eFPGAs have stood apart from the competition in terms of flexibility and ease of use,” said Yoan Dupret, who is in charge of business development at Menta. “The boost in performance and support of additional process nodes with our next generation of eFPGAs will bring the benefits of post production RTL modification to a wider range of applications. This is a game changer for any engineering team aiming to meet compressed time-to-market windows with the confidence that their systems can accommodate evolving standards or additional customer-defined features.”
Optimized performance, density and power consumption
Version 4 of Menta’s custom and pre-defined eFPGA IP cores will benefit from a boost in performance, area usage, and lower power consumption. For example, on a circuit with 15k equivalent programmable logic gates (including 1056 LUT6 and six 18bits MAC DSP) intended for TSMC 28nm HPM process, the area is less than 0.9mm², the static power consumption is 0.47mW and the single stage control logic runs at 740MHz while the LUT utilization is greater than 90%. It is always difficult to compare programmable logic cores since the LUT definition and architectures are different. However, Menta eFPGAs feature better static power vs frequency than competition, and is unique in offering fault coverage greater than 99.6%.
Flexible design for any SOC enabled by comprehensive EDA support tools
Menta pre-defined eFPGAs have from 7k-60k equivalent ASIC gates, plus DSP blocks. The IP cores are delivered as hard macros with optimized arrays sizes. In addition, Menta can deliver custom IP cores with embedded logic blocks (eLB), embedded custom blocks (eCB), and embedded memory blocks (eMB), each of which are customizable in type, number and size to address various markets and applications. Menta provides Origami Designer to define in the simplest way the custom IP based on designers’ RTL. The eFPGA IP cores are designed for standard test compatibility with all common ASIC and SOC test solutions.
Menta’s also provides customer support with Origami Programmer, a proven EDA tool that supports design from HDL design to bitstream with synthesis, mapping, place and route. Origami Programmer includes synthesis to allow RTL applications in VHDL, Verilog or SystemVerilog, as well as SDC support for application design constraints. Additionally, timing analyses tools enhance engineer experience and facilitate designs.
Availability
Menta’s eFPGA IP cores and associated software are available now. For more information, please visit www.menta-efpga.com, or contact our customer support team at Email Contact.
About Menta
Menta is a privately held company based in Montpellier, France. The company provides embedded FPGA (eFPGA) technology for SoC, ASIC or SASSP designs. Menta's programmable logic architecture is based on scalable, customizable and easily programmable architecture created to provide programmability for next-generation ASIC design with the benefits of eFPGA design flexibility. For more information, visit the company website at: www.menta-efpga.com
Origami Designer, Origami Programmer and eFPGA Core IP are registered trademarks of Menta SAS. All other trademarks and tradenames are the property of their respective holders.
