Growing RISC-V Ecosystem to Share New Developments and Momentum

Growing RISC-V Ecosystem to Share New Developments and Momentum at DAC 2018

RISC-V Foundation and members to exhibit and participate in a variety of speaking tracks

SAN FRANCISCO — (BUSINESS WIRE) — June 12, 2018 — The RISC-V Foundation:

WHERE: DAC 2018, West Hall, Level Two at Booth #2638; Moscone Center West, 800 Howard St, San Francisco, CA 94103

WHEN: Sunday, June 24 to Wednesday, June 27, 2018

WHAT: The RISC-V Foundation will share updates on new projects, products and implementations from its expansive membership at DAC 2018. The RISC-V Foundation will be exhibiting with member companies Imperas Software, Microsemi, SiFive, Syntacore, UltraSoC and Western Digital at Booth #2638.

The RISC-V Foundation will be hosting a scavenger hunt for attendees to learn more about members at the booth. Scavenger hunt participants will be entered into drawings to win prizes from members. At its booth the RISC-V Foundation will also be hosting presentations from member companies each day of the show. The schedule of poster presentation sessions at the booth is as follows:

Monday, June 25, 2018:

RISC-V ISA & Foundation Overview
- When: 11 a.m. – noon PT
- Who: Rick O’Connor, RISC-V Foundation
From Lab to Fab: An IP Story
- When: Noon – 1 p.m. PT
- Who: Drew Barbier, SiFive
Panel: Meet the RISC-V Members at DAC 2018
- When: 1 p.m. – 2 p.m. PT
Fueling the RISC-V Ecosystem With Microsemi’s Mi-V Programmable Solutions
- When: 2 p.m. – 3 p.m. PT
- Who: Ted Marena, Microsemi
Machine Learning With RISC-V
- When: 3 p.m. – 4 p.m. PT
- Who: Filip Blagojevic, Western Digital
It’s Not Just the Core, It’s the System: Processor Trace in a Holistic World
- When: 4 p.m. – 4:30 p.m. PT
- Who: Randy Fish, UltraSoC
RISC-V Virtual Platforms, Simulators and Software Tools
- When: 4:30 – 5 p.m. PT
- Who: Simon Davidmann, Imperas
Enabling Innovation in Embedded and Enterprise Data-Centric Architectures
- When: 5 p.m. – 6 p.m. PT
- Who: Zvonimir Bandic, Western Digital

Tuesday, June 26, 2018:

RISC-V ISA & Foundation Overview
- When: 11 a.m. – noon PT
- Who: Rick O’Connor, RISC-V Foundation

It’s Not Just the Core, It’s the System: Processor Trace in a Holistic World
- When: Noon – 1 p.m. PT
- Who: Randy Fish, UltraSoC
Panel: The Key Role for the Commercial Software Tools Ecosystem for RISC-V
- When: 1 p.m. – 2 p.m. PT
RISC-V Support for Persistent Memory Systems
- When: 2 p.m. – 3 p.m. PT
- Who: Matheus Ogleari, Western Digital
RISC-V Virtual Platforms, Simulators and Software Tools
- When: 3 p.m. – 4 p.m. PT
- Who: Simon Davidmann, Imperas
SCRx Family of the RISC-V Compatible Processor IP
- When: 4:30 p.m. – 5 p.m. PT
- Who: Alexander Redkin, Syntacore
Keynote: Vision and History of RISC-V
- When: 5 p.m. – 6 p.m. PT
- Who: Yunsup Lee, SiFive

Wednesday, June 27, 2018:

Fueling the RISC-V Ecosystem with Microsemi’s Mi-V Programmable Solutions
- When: 11 a.m. – Noon PT
- Who: Ted Marena, Microsemi
SCRx Family of the RISC-V Compatible Processor IP
- When : Noon – 1 p.m. PT
- Who : Alexander Redkin, Syntacore
Panel: New Markets and Applications for RISC-V
- When: 1 p.m. – 2 p.m. PT
Panel: Meet the RISC-V Foundation Board of Directors
- When: 2 p.m. – 3 p.m. PT
RISC-V ISA & Foundation Overview
- When: 3 p.m. – 4 p.m. PT
- Who: Rick O’Connor, RISC-V Foundation

DAC has invited the RISC-V Foundation to present the RISC-V Ecosystem – Reshaping the CPU Landscape workshop on Sunday, June 24 from 1 p.m. to 4 p.m. PT in room 3018. The sessions will detail how the free and open RISC-V instruction set architecture (ISA) is creating a paradigm shift in industry, reinvigorating semiconductor design and reshaping traditional business models. Sessions will include:

RISC-V ISA and Foundation Overview
- Speaker: Rick O’Connor, RISC-V Foundation

RISC-V – A Diversity of Core and Accelerator Choices
- Speaker: Markus Levy, NXP

RISC-V OS Landscape
- Speaker: Palmer Dabbelt, SiFive

Designing a Custom RISC-V Core Using Chisel
- Speaker: Alex Badicioiu, NXP

Members of the RISC-V Foundation are participating in additional sessions including:

Core Choices: How To Navigate The Brave New World Of IP (Panel)
- When: Tuesday, June 26 from 3:00 p.m. – 3:45 p.m. PT (Booth 2161)
- Key Panelist: Rick O’Connor, RISC-V Foundation
- Other Panelists: John Ronco, Arm; Majid Bemanian, MIPS Technologies; and Markus Levy, NXP Semiconductors
- Moderator: Junko Yoshida, EE Times
A New Golden Age For Computer Architecture: Domain Specific Accelerators And Open RISC-V (Keynote)
- When: Wednesday, June 27 from 9:20 a.m. – 10:00 a.m. PT (Room 3008)
- Speaker: David A. Patterson, vice chair of the RISC-V Foundation Board of Directors; Google Inc. and University of California, Berkeley

PULP-HD: Accelerating Brain-Inspired High-Dimensional Computing on a Parallel Ultra-Low Power Platform (Research Reviewed)
- When: Wednesday, June 27 from 3:30 p.m. – 5:30 p.m. (Room 3022)
- Speaker: Fabio Montagna, University of Bologna, Italy
Computing Minus Moore’s Law = ?!?! (Panel)
- When: Wednesday, June 27 from 4:30 p.m. – 5:30 p.m. PT (Room 3024)
- Key Panelist: Krste Asanovic, chairman of the RISC-V Foundation Board of Directors; University of California, Berkeley and SiFive
- Other Panelists: Kathy Wilcox, Advanced Micro Devices; David Brooks, Harvard University and Facebook; Yuan Xie, University of California, Santa Barbara
- Moderator: Todd Austin, University of Michigan

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