The Tool, the first deliverable in FSA's IPecosystem Tool Suite, collects information about an IP vendor, its design methodology and the IP family under evaluation to develop a risk assessment profile across seven criteria: IP design, integration, verification, process technology, product documentation, reliability and test.
The latest version includes several enhancements that improve ease-of-use and increase communication for integrators and vendors, as well as foundries, including:
-- Custom Questionnaire - A new custom questionnaire allows vendors to add questions pertaining to specific IP. The integrator completes those questions and can weight specific factors. This benefit facilitates vendors communicating a message to an integrator about a specific IP family.
-- Answer Verification - A filter added to the Hard IP summary page allows an answer to be verified. This feature allows vendors and integrators with long-term relationships to add a yes/no confidence level, reflected in a risk profile.
-- Feedback Button - The feedback loop button has been enhanced so integrators can provide feedback directly to the vendor, aiding the vendor in evaluating additional improvements to its IP.
-- ChipEstimate.com Collaboration - Vendors now have an option to upload their Tool "risk profiles" to Chip Estimate's IP portal. In addition, Chip Estimate users may request a vendor's risk profiles or request that a vendor complete the Tool for their IP or family of IP within their portfolio. Please see related announcement for further information on this collaboration.
IP integrators, from fabless, integrated device manufacturer (IDM) and design companies, that purchase third-party IP or evaluate internal IP for reuse, gain increased intelligence utilizing the Tool.
"As a system-on-chip (SoC) pioneer, Avago Technologies understands the importance of IP quality. FSA's Hard IP Quality Risk Assessment Tool complements our IP evaluation process and should further enhance our established ability to supply highly reliable ASICs for networking, computing, and storage applications," said James Stewart, vice president and general manager of Avago Technologies ASIC products division. "Customers will gain another measure of confidence knowing that such collective support can only lead to better, more reliable products to help them meet time-to-market goals."
"The latest version of this tool helps to expedite SoC design by setting a quality risk profile for IP," said Craig Hunter, Power Embedded Core project manager for Freescale Semiconductor. "Establishing a common benchmark for interchangeable IP can help boost the overall quality of SoC designs."
Demonstrations at FSA Suppliers Expo
FSA will be conducting demonstrations of the Hard IP Quality Risk Assessment Tool in booth 408 of the FSA Suppliers Expo and Conference on September 12 from 10:00 a.m. to 11:00 a.m. and from 3:00 p.m. to 4:00 p.m. at the Santa Clara Convention Center in Santa Clara, Calif.
Pricing and Availability
The Tool is now available complimentary to the industry. To download version 3.0 and view an online demonstration of the tool, please visit www.fsa.org/IPecosystem.
About FSA
FSA is the voice of the global fabless business model. Incorporated in 1994, FSA positively impacts the growth and return on invested capital of this business model to enhance the environment for innovation. It provides a platform for meaningful global collaboration between fabless companies and their partners; identifies and articulates opportunities and challenges to enable solutions; and provides research, resources, publications and survey information. Members include fabless companies and their supply chain and service partners, representing more than 21 countries across the globe. www.fsa.org.
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