Engineering Luminary Discusses SoC Development with High-Speed Interface Solutions

PALO ALTO, Calif., April 15 /PRNewswire/ -- Brian Gardner, vice president of IP products at Denali Software, Inc., will speak on a panel titled, "Silicon Subsystems: How to Develop SoCs Faster and With Lower Risk," during the Intellectual Property (IP) Symposium, an event sponsored by CMP. The panel session will be held Tuesday, April 15, at the Fairmont Hotel in San Jose, California. This panel addresses key areas pertaining to system-on-chip (SoC) development such as integration issues, improving data throughput, and lowering schedule risks. This panel will appeal to systems architects, SoC project managers, senior engineering and engineering management including directors and vice presidents of Engineering, Chief Technology Officers, Fellows, and members of Technical Staff.

Additionally, on the same afternoon agenda, Mr. Gardner will present "Tackling Essential Issues for Successful IP Deployment and Integration in the SoC Era," covering key enabling ingredients for SoC designs and the implications of IP development infrastructures. The presentation will highlight various IP deployment strategies and verification methodologies which help to realize the promise of faster time to market and reduced risk.

     WHO:      Brian Gardner, vice president of IP products at Denali Software

     WHAT:     "Silicon Subsystems: How to Develop SoCs Faster and With Lower
               Risk," is a key panel during the IP Symposium, addressing
               products and services for subsystems, aimed at removing
               integration issues, improving data throughput, and lowering
               schedule risks facing many development teams today. In
               particular, the panel will discuss what subsystems are and how
               they help successful SoC development.

     WHEN:     Tuesday, April 15, 2008 - 1:45pm - 2:45pm

     WHERE:    Fairmont, San Jose, California - Hillsborough Salon

     WHO:      Brian Gardner, vice president of IP products at Denali Software

     WHAT:     "Tackling Essential Issues for Successful IP Deployment and
               Integration in the SoC Era." This presentation will discuss
               third party IP emerging trend as a key enabling ingredient for
               SoC designs and the implications of IP development
               infrastructures, as well as cover various IP deployment
               strategies and verification methodologies. For more information,
               visit 
www.eetimes.semiconductor.com/agenda.asp 
     WHEN:     Tuesday, April 15, 2008 - 3:00pm - 4:00pm

     WHERE:    Fairmont, San Jose, California - Glen Ellen Salon

About Denali Software

Denali Software, Inc. is a world-leading provider of electronic design automation (EDA) software and intellectual property (IP) for system-on-chip (SoC) design and verification. Denali delivers the industry's most trusted solutions for deploying PCI Express, NAND Flash and DDR DRAM subsystems. Developers use Denali's EDA, IP and services to reduce risk and speed time-to-market for electronic system and chip design. Denali is headquartered in Sunnyvale, California and has offices around the world to serve the global electronics industry. More information about Denali, its products and services is available at http://www.denali.com.

Denali and the Denali logo are trademarks of Denali Software Inc. All other trademarks are the property of their respective owners.

     Editorial Contact:
     Pierre Golde
     (408) 743-4262
     Denali Software, Inc.
     pgolde@denali.com

Web site: http://www.denali.com/