Founded in 1999, Avery Design Systems, Inc. enables system and SOC design teams to achieve dramatic functional verification productivity improvements through the use of formal analysis applications for automatic property and coverage generation, X verification, and RT-level DFT at-speed testability analysis; robust core-through-chip-level Verification IP for PCI Express, USB, AMBA, and MIPI standards; and scalable distributed parallel logic simulation. The company is a member of the Synopsys SystemVerilog and VMM Catalyst Programs, Mentor Graphics Modelsim Value Added Partnership (VAP) program, and has established numerous Avery Design VIP partner program affiliations with leading IP suppliers. More information about the company may be found at www.avery-design.com.
Contact:
Avery Design Systems
Chris Browy, 978-689-7286
Email Contact
