SAN JOSE, CA -- (Marketwire) -- Oct 04, 2012 -- Distinguished UC-Berkeley Professor Jan M. Rabaey will deliver the keynote at a Low-Power Technology Summit sponsored by Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design innovation. Rabaey, author of "Low-Power Design Essentials," will address power issues that impact today's chip designers at the one-day technical conference on Oct. 18.

There is no fee to attend.

WHERE:
Cadence Design Systems, Building 10 auditorium
2655 Seely Ave., San Jose, Calif., 95134

WHEN:
Oct. 18, 2012 - 8:30 a.m. to 5 p.m.

WHAT:
In addition to the keynote with Rabaey, attendees will see presentations including "Low-Power Design with ARM® Physical IP and POP™ IP," by Sathya Subramanian of ARM, and "Low-Power Design Experiences on Freescale Kinetis MCU Family," by Anis Jarrar of Freescale. Additionally, attendees will have lunch with Cadence R&D members, Dr. Qi Wang of Cadence will deliver an update on power format standards, and there will be an afternoon panel discussion on low-power techniques.

For the complete agenda, visit the Cadence Web site. Journalists interested in attending should contact Dean Solov at Cadence by phone (408-944-7226) or email ( Email Contact)

About Cadence

Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software, hardware, IP, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at www.cadence.com.

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For more information, please contact:
Dean Solov
Cadence Design Systems

Email Contact
(408) 944-7226 

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