The results presented in this session focus on sequential equivalence checking, and for this purpose, isomorphic proof obligations are identified. If two proof obligations are isomorphic, then the tool only needs to derive a formal proof for one of the obligations, thus reducing the total number of proof obligations that need to be considered. In this presentation, we look at a variety of industrial equivalence checking testcases and demonstrate that:
- This simulation-based approach can identify the isomorphic proof obligations in mere seconds.
- On average, the number of proof obligations is reduced by 61%.
- The time needed to prove the proof obligations is reduced by 60%.
About Calypto’s Products
Catapult high-level synthesis, SLEC® (Sequential Logic Equivalence Checking) and PowerPro platforms are used to design, verify and optimize complex SoC and FPGA designs by seven out of the top ten semiconductor companies and over 100 leading consumer electronics companies worldwide. Calypto’s products enable engineers to dramatically improve design quality and reduce power consumption of their SoC while significantly reducing overall design and verification time.
About Calypto
Calypto® Design Systems, Inc. is the leader in ESL hardware design and RTL power optimization. Calypto, whose customers include Fortune 500 companies worldwide, is a member of the ARM Connected Community, Cadence Connections program, the IEEE‐SA, Synopsys SystemVerilog Catalyst Program, the Mentor Graphics OpenDoor program, Si2 and is an active participant in the Power Forward Initiative. Calypto has offices in Europe, India, Japan and North America.
Catapult, Calypto, PowerPro and SLEC are registered trademarks of Calypto Design Systems Inc. All other trademarks are property of their respective owners.
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Cayenne Communications
Linda Marchant, 919-451-0776
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