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Calypto Expands Participation at DAC 2013 in Austin, TX

SAN JOSE, Calif., – May 29, 2013 –Calypto® Design Systems, Inc., the leader in electronic system level (ESL) hardware design and register transfer level (RTL) power optimization, today announced  increased participation in DAC 2013.  Calypto’s three product families (PowerPro®, Catapult® and SLEC®) offer customers solutions ranging from RTL power reduction to C++/ SystemC high-level synthesis.

HIGHLIGHTS

–     Tuesday, June 4, 12:00 - 1:30  – Practical Consideration in a Sequential Power Optimization Flow, Cisco

–     Wednesday, June 5, 12:00 - 1:30  – Power Regression Methodology Reduces Dynamic Power by 20 Percent, AMD

–     Wednesday,  June 5, 2:00 -  4:00  – Reducing Design and Debug Time with Synthesizable TLM, location: 9ABC

About Calypto’s Products

Catapult high-level synthesis, SLEC® (Sequential Logic Equivalence Checking) and PowerPro platforms are used to design, verify and optimize complex SoC and FPGA designs by seven out of the top ten semiconductor companies and over 100 leading consumer electronics companies worldwide. Calypto’s products enable engineers to dramatically improve design quality and reduce power consumption of their SoC while significantly reducing overall design and verification time.

About Calypto

Calypto® Design Systems, Inc. is the leader in ESL hardware design and RTL power optimization.  Calypto, whose customers include Fortune 500 companies worldwide, is a member of the ARM Connected Community, Cadence Connections program, the IEEEā€SA, Synopsys SystemVerilog Catalyst Program, the Mentor Graphics OpenDoor program, Si2 and is an active participant in the Power Forward Initiative. Calypto has offices in Europe, India, Japan and North America.  

Catapult, Calypto, PowerPro and SLEC are registered trademarks of Calypto Design Systems Inc. All other trademarks are property of their respective owners.