REMONT, Calif., July 9, 2013 – VIA Telecom, a leading provider of CDMA baseband processor solutions, has chosen ClioSoft SOS for its analog/ mixed-signal design teams. ClioSoft, Inc. is the developer of the premier hardware configuration management (HCM) solutions for the electronics design industry.
VIA Telecom selected ClioSoft SOS as their major collaboration platform for its easy-to-use model and the seamless integration with the Cadence Virtuoso® platform and its related products. The fast emerging market of mobile communication IC requires a shortened design cycle and a high level of multiple-IP integration, but no compromise on the robustness of products. ClioSoft SOS empowers the circuit design team with the flexibility of information sharing and design collaboration. This greatly accelerates the process of IP assembly and circuits, or system-level verification, while not sacrificing the quality of the design.
“VIA Telecom believes that ClioSoft SOS will help the project execution effectively and improve the efficiency of design data and IP management,” said Shih-An Yu, Design Manager at VIA Telecom.
“We are proud to help VIA Telecom collaborate effectively and enhance the sharing and management of design data and IP across the enterprise,” said Srinath Anantharaman, founder and CEO of ClioSoft.
About ClioSoft:
ClioSoft is the premier developer of hardware configuration management (HCM) solutions. The company's SOS Design Collaboration platform is built from the ground up to handle the requirements of hardware design flows. The SOS platform provides a sophisticated multi-site development environment that enables global team collaboration, design and IP reuse, and efficient management of design data from concept through tape-out. Custom engineered adaptors seamlessly integrate SOS with leading design flows – Agilent’s Advanced Design System (ADS), Cadence’s Virtuoso® Custom IC, Mentor’s Pyxis Custom IC Design, Synopsys’ Galaxy Custom Designer and Laker™ Custom Design. The Visual Design Diff (VDD) engine enables designers to easily identify changes between two versions of a schematic or layout or the entire design hierarchy below by graphically highlighting the differences directly in the editors.
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Note to Editors :
A Mandarin translation of this announcement is available from Asia-Pacific contacts.
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