Now available in the Vivado Design Suite 2016.1, SmartConnect technology solves the system interconnect bottlenecks for high performance, multi-million system logic cell designs
SAN JOSE, Calif., April 19, 2016 — (PRNewswire) — Xilinx, Inc. (NASDAQ: XLNX) today announced the 2016.1 release of the Vivado® Design Suite HLx Editions, with extensions to the SmartConnect technology, delivering unprecedented levels of performance for the UltraScale™ and UltraScale+ device portfolios. In the 2016.1 release, Vivado Design Suite includes extensions to the SmartConnect technology, solving the system interconnect bottlenecks on high density, multi-million system logic cell designs. As a result, both UltraScale and UltraScale+ device portfolios now deliver an additional 20-30% performance at high utilization.Logo - http://photos.prnewswire.com/prnh/20020822/XLNXLOGO
The Xilinx UltraScale+ portfolio is the only FinFET based programmable technology available in the industry. It includes Zynq®, Kintex®, and Virtex® UltraScale+ devices, and delivers 2-5X performance/watt improvement over 28nm offerings, enabling market-leading applications such as 5G wireless, software-defined networks and next-generation advanced driver-assistance systems.
The Xilinx SmartConnect technology includes a system interconnect IP, as well as new optimizations enabled by the UltraScale+ silicon innovations:
- The AXI SmartConnect IP: Xilinx's new system connectivity generator, integrating peripherals to the user design. SmartConnect creates a custom interconnect that best matches the user's system performance requirements, thereby achieving higher system throughput at a lower area and power footprint. The AXI SmartConnect IP is available in Early Access via Vivado IP Integrator in the 2016.1 release of the Vivado Design Suite.
- Time borrowing and useful skew optimization: These optimizations are enabled by the new UltraScale+ fine-grain clock delay insertion capability. These fully automated features mitigate large wire delays and deliver designs running at higher clock frequencies, by shifting available timing slack from the fastest paths to the critical paths of the design.
- Pipeline analysis and retiming: These techniques allows designers to further increase performance, by adding extra pipeline stages in the design and applying automatic register retiming optimization.
Availability
The Vivado Design Suite HLx Editions and embedded software development tools 2016.1 release are now available for download. To learn more about Xilinx software development environments visit the Xilinx Software Developer Zone. To learn more about SmartConnect technology, download the backgrounder and visit http://www.xilinx.com/products/technology/smart-connect.html.
About the Xilinx UltraScale+ Portfolio
The 16nm UltraScale+ family of FPGAs, 3D ICs, and MPSoCs, combines new memory, 3D-on-3D and multi-processing SoC (MPSoC) technologies enabling an even higher level of performance and integration, and includes the SmartConnect interconnect optimization technology. Optimized at the system level, the UltraScale+ portfolio delivers value far beyond a traditional process node migration – providing 2–5X greater system level performance/watt over 28nm devices, far more systems integration and intelligence, and the highest level of security and safety.
About Xilinx
Xilinx is the leading provider of All Programmable FPGAs, SoCs, MPSoCs, and 3D ICs. Xilinx uniquely enables applications that are both software defined and hardware optimized – powering industry advancements in Cloud Computing, SDN/NFV, Video/Vision, Industrial IoT, and 5G Wireless. For more information, visit www.xilinx.com.
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© Copyright 2016 Xilinx, Inc. Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. All other trademarks are the property of their respective owners.
Xilinx
Silvia E. Gianelli
(408) 626-4328
silvia.gianelli@xilinx.com
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SOURCE Xilinx, Inc.
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