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Rambus to Showcase SerDes and Memory PHY Solutions at DesignCon

Experts to present two technical sessions addressing verification and power efficiency and additional technical trainings explore system design challenges for memory and serial links

SUNNYVALE, Calif. — (BUSINESS WIRE) — January 24, 2017 — Rambus Inc. (NASDAQ: RMBS):

Who:  

Rambus Inc. (NASDAQ: RMBS)

 
Where: DesignCon
Booth #833
Santa Clara Convention Center
5001 Great America Pkwy
Santa Clara, CA 95054
 
When: January 31 – February 2, 2017 (Conference)
February 1 – 2, 2017 (Expo)

Join Rambus at DesignCon for product demonstrations showcasing its comprehensive suite of Ethernet, PCIe and DDRn IP solutions to solve today’s most challenging data center and networking applications. Rambus technical experts, executives and partners will also be holding a series of talks and technical training sessions listed below.

Rambus Technical Session Details:
Title: Power Delivery Network Design and Optimization for High-Speed Systems with Si Interposer
Date: Wednesday, February 1, 2017
Time: 9:00 am – 9:45 am
Location: Ballroom A
Speaker: Wendem Beyene, Technical Director, Rambus

Title: Methodology for Reusing the Verification Tests and Efforts Beyond Pre-silicon Verification
Date: Thursday, February 2, 2017
Time: 3:00 pm – 3:45 pm
Location: Ballroom C
Speakers: Dinesh Malviya, Sr. Manager Engineering, Rambus; Sujith Hiremath, Senior Member of Technical Staff - Verification, Rambus

Rambus Training Sessions:
Title: An 8b ADC for a 56Gbps PAM4 Receiver
Date: Wednesday, February 1, 2017
Time: 9:20 am – 10:00 am
Location: Great America 3
Speakers: Kenneth C. Dyer, Senior Principal Engineer Architect, Rambus; Shankar Tangirala, Principal Design Engineer, Rambus

Title: ADC-Based Link Architecture for Multilevel Signaling at 56G
Date: Wednesday, February 1, 2017
Time: 10:15 am – 10:55 am
Location: Great America 3
Speakers: Masum Hossain, Senior Principal Engineer, Rambus; Nhat Nguyen, Sr. Director of Engineering, Architecture & Design, Rambus

Title: PCI Express PHY and Controller Integration at Gen4: PLDA’s Proven Methodology for First-Time Silicon Success
Date: Wednesday, February 1, 2017
Time: 11:05 am – 11:45 am
Location: Great America 3
Speaker: Trupti Gowda, Field Application Engineer, PLDA Inc.

Title: Design and Modelling of 2.5D HBM2 Interposer System
Date: Wednesday, February 1, 2017
Time: 2:00 pm – 2:40 pm
Location: Great America 3
Speaker: Yuri Tretiakov, Principal Engineer, Systems / IC Package Design, Rambus

Title: SI and PI Challenges of a 2.5D HBM2 Interposer System
Date: Wednesday, February 1, 2017
Time: 2:50 pm – 3:30 pm
Location: Great America 3
Speakers: Ravi Kollipara, Technical Director, Engineering, Rambus; Joohee Kim, Senior Member of Technical Staff II, Rambus

Title: HBM2 Controller and PHY Integration
Date: Wednesday, February 1, 2017
Time: 3:45 pm – 4:25 pm
Location: Great America 3
Speaker: Brian Daellenbach, President, Northwest Logic

For additional information on Rambus products and solutions, please visit rambus.com.

Follow Rambus:

Company website:  rambus.com
Rambus blog:  rambusblog.com
Twitter:  @rambusinc
LinkedIn:  www.linkedin.com/company/rambus
Facebook:  www.facebook.com/RambusInc

About Rambus Inc.

Rambus creates innovative hardware and software technologies, driving advancements from the data center to the mobile edge. Our chips, customizable IP cores, architecture licenses, tools, software, services, training and innovations improve the competitive advantage of our customers. We collaborate with the industry, partnering with leading ASIC and SoC designers, foundries, IP developers, EDA companies and validation labs. Our products are integrated into tens of billions of devices and systems, powering and securing diverse applications, including Big Data, Internet of Things (IoT), mobile, consumer and media platforms. At Rambus, we are makers of better. For more information, visit rambus.com.


Contact:

Rambus Corporate Communications
Agnes Toan, 408-462-8905
Email Contact