To address the many technical challenges of 7nm design, the Virtuoso Advanced-Node Platform offers a variety of layout capabilities, including advanced editing with multi-pattern color awareness, FinFET grids, and module generator (ModGen) device arrays. Additionally, customers can take advantage of variation analysis in their circuit design flows utilizing Monte Carlo analysis across corners to address variability with the Spectre® Accelerated Parallel Simulator, the Virtuoso ADE Product Suite and the Virtuoso Schematic Editor.
For more information on how the expanded Virtuoso Advanced-Node Platform is optimized for the 7nm process, please visit www.cadence.com/go/virtuosoadvancednode.
"As a leader in mobile computing, we require the highest performance, lowest power and highest density possible to deliver innovative, advanced-node designs," said Ching San Wu, general manager of Analog Design and Circuit Technology at MediaTek. "Through our strong collaboration and continued partnership with Cadence, we have been able to develop and deploy a custom design methodology based on the Virtuoso Advanced-Node Platform. With our recent successful tapeout, we took advantage of its many unique capabilities designed to manage the challenges presented at 7nm."
Key features in the updated Virtuoso Advanded-Node Platform include:
- Multi-patterning and color-aware layout: Provides essential new support of a variety of fully colored "multi-patterned" custom design flows, which are a baseline requirement for the 7nm process and enable users to be more productive in their designs.
- ModGen device arrays: Offers designers a set of modules that have been co-developed in close collaboration with key partners to improve designer productivity and mitigate layout complexities at the 7nm process node.
- Automated FinFET placement: Provides automatic FinFET grid placement that simplifies the overall FinFET-based coloring design methodologies needed at 7nm. By adhering to 7nm process constraints, the Virtuoso Advanced-Node Platform greatly simplifies layout creation and minimizes errors that can be pervasive when designing at 7nm, while decreasing layout design time by up to 50 percent on custom digital and analog blocks.
- Variation analysis: Enables high-performance Monte Carlo analysis targeting FinFET technology and high-sigma analysis, which can reduce the overall time to run simulations by a factor of 10.
"Through constant innovation and strategic partnerships with industry leaders, Cadence has solidified its leading role in providing advanced-node custom design tools," said Tom Beckley, senior vice president and general manager, Custom IC & PCB Group at Cadence. "Through our extensive work with customers such as MediaTek, we've been able to validate that our approaches greatly reduce the overhead inherent in designing at 7nm in order to help deliver the best possible silicon. We currently have many customers that have completed successful tapeouts and delivered production designs using the Virtuoso Advanced-Node Platform."
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