SAN JOSE, CA--(Marketwired - June 14, 2017) -
What: The 54th Design Automation Conference 2017, the premier conference for design and automation of electronic systems.
Who: Andes Technology Corp. Senior Vice President USA, Emerson Hsiao and VP Sales USA, Nancy Gomes will describe the new 64-bit NX25 CPU based on Andes innovative V5 instruction set architecture (ISA). Andes V5 adopts RISC-V Instruction Set Architecture developed at the University of California Berkeley while adding the complement of peripherals, bus fabric, and software development tools needed to design a RISC V solution.
Why: Andes Technology Corp. is augmenting its very successful and highly demanded embedded processor cores with RISC-V cores to support the RISC-V design community. Andes brings its success in Asia to U.S. fabless and fablite semiconductor companies enabling next generation SoC designs with the most complete RISC-V ecosystem, unique functionality including a complete AXI and AHB bus fabric IP to reduce design time for integrating the peripherals required by the CPU.
Who should attend: SoC and ASIC chip architects, designers, and software developers.
When: Andes executives will be available from 10:00 AM 6:00 PM Monday through Wednesday June 19, 20, and 21, at Booth 1820. To schedule a meeting, contact Nancy Gomes ( Email Contact).
Where: The Neal Kocurek Memorial Austin Convention Center 500 E Cesar Chavez St, Austin, TX 78701.
Media Contact: Jonah McLeod Andes Technology Corporation 510 449 8634 Email Contact