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LIVE WEBINAR: Fast Track to Riviera-PRO, Part 1: Design Entry & Simulation
Presenter: Sunil Sahoo, Sr. Corporate Applications Engineer
Thursday, August 17, 2017
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EU TIME ZONE
Time: 3:00 PM – 4:00 PM (CEST)
Thursday, August 17, 2017
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US TIME ZONE
Time: 11:00 AM – 12:00 PM (PDT)
Thursday, August 17, 2017
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Abstract:
Riviera-PRO™ Advanced Verification Platform addresses the verification needs of engineers crafting tomorrow's cutting-edge FPGA and SoC devices. Riviera-PRO enables the ultimate testbench productivity, reusability, and automation by combining the high-performance simulation engine, advanced debugging capabilities at different levels of abstraction, and support for the latest Language and Verification Library Standards.
This first webinar of a two-part "Fast Track" series is designed to help functional verification engineers get up to speed quickly with Design Management and Design Entry in Riviera-PRO. Includes tips and tricks to enable easier debugging of designs. Also covers how to run Simulations and handling waveforms.
Agenda:
- Introduction
- Live Demo
- Conclusion
- Q&A
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LIVE WEBINAR: Fast Track to Riviera-PRO, Part 2: Advanced Debugging, Code Coverage and Scripting
Presenter: Sunil Sahoo, Sr. Corporate Applications Engineer
Thursday, August 31, 2017
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EU TIME ZONE
Time: 3:00 PM – 4:00 PM (CEST)
Thursday, August 31, 2017
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US TIME ZONE
Time: 11:00 AM – 12:00 PM (PDT)
Thursday, August 31, 2017
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Abstract:
Riviera-PRO™ Advanced Verification Platform addresses the verification needs of engineers crafting tomorrow's cutting-edge FPGA and SoC devices. Riviera-PRO enables the ultimate testbench productivity, reusability, and automation by combining the high-performance simulation engine, advanced debugging capabilities at different levels of abstraction, and support for the latest Language and Verification Library Standards.
This second webinar of a two-part "Fast Track" series is designed to help functional verification engineers get up to speed quickly. In this webinar, you'll learn about more debugging tips and we'll also cover Tracing Logic and how to run code coverage in Riviera-PRO. We'll also take a look at Plots - a new way of analyzing results.
Agenda:
- Introduction
- Live Demo
- Conclusion
- Q&A
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Presenter Bio:
Sunil Sahoo provides support for customers exploring simulation tools as an Aldec Applications Engineer. His practical engineering experience includes areas in, Digital Designing, Functional Verification and Wireless Communications. He has worked in wide range of engineering positions that include Digital Design Engineer Verification Engineer and Applications Engineer. He received his B.S. in Electronics and Communications Engineering from VIT University, India in 2008 and M.S in Computer Engineering from Villanova University, PA in 2010.
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To view all upcoming Aldec Events and Webinars, please visit our events page
here.
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Aldec is a global industry leader in Electronic Design Verification and offers a patented technology suite including: RTL Design, RTL Simulators, Hardware-Assisted Verification, Embedded, SoC and ASIC Prototyping, Design Rule Checking, CDC Verification, IP Cores, DO-254 Functional Verification and Military/Aerospace solutions.
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