Foundation members demo RISC-V-based implementations
(BUSINESS WIRE) — August 16, 2017 — RISC-V Foundation:
|
WHERE: |
Hot Chips 29, Flint Center for the Performing Arts, 21250 Stevens Creek Blvd, Cupertino, Calif., 95014 | ||||||
|
WHEN: |
Sunday, Aug. 20 to Tuesday, Aug. 22, 2017 | ||||||
|
WHAT: |
RISC-V® Foundation will exhibit at Hot Chips 29, showcasing the momentum of its Instruction Set Architecture (ISA), the industry’s first open, free architecture. RISC-V founding member, SiFive, will host a session detailing the industry’s first open-source RISC-V system-on-chip (SoC). Representatives from UC San Diego, Cornell and the University of Michigan will speak about Celerity, an open source RISC-V SoC with a neural network accelerator fabric. Speaking sessions include: | ||||||
-
SiFive Freedom SoCs: Industry’s First Open-Source RISC-V Chips
- When: Monday, Aug. 21 from 11:30 a.m. to 12:30 p.m. PT
- Who: Yunsup Lee at SiFive
-
Celerity: An Open Source RISC-V Tiered Accelerator Fabric
- When: Monday, Aug. 21 from 4:15 p.m. to 6:15 p.m. PT
- Who: Scott Davidson at UC San Diego, Khalid Al-Hawaj at Cornell and Austin Rovinski at the University of Michigan
Founding member Gray Research LLC will present a poster on GRVI Phalanx, a 1,680-core RISC-V FPGA accelerator which integrates the greatest number of 32-bit RISC processors ever implemented on a chip in any technology. Poster details include: -
GRVI Phalanx: A Massively Parallel RISC-V FPGA Accelerator
Framework: A 1680-core, 26 MB SRAM Parallel Processor Overlay on
Xilinx UltraScale+ VU9P
- When: Tuesday, Aug. 22
- Who: Jan Gray at Gray Research
Additionally, founding member Microsemi will be showcasing information about its Creative Development Board at the RISC-V table. The board enables the quick development of RISC-V projects and will be available for purchase at Future Electronics in September 2017.
1 | 2 Next Page »
