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RISC-V Foundation to Showcase Growth of New Architecture at Hot Chips 29

Foundation members demo RISC-V-based implementations

(BUSINESS WIRE) — August 16, 2017 — RISC-V Foundation:

           

WHERE:

Hot Chips 29, Flint Center for the Performing Arts, 21250 Stevens Creek Blvd, Cupertino, Calif., 95014
 

WHEN:

Sunday, Aug. 20 to Tuesday, Aug. 22, 2017
 

WHAT:

RISC-V® Foundation will exhibit at Hot Chips 29, showcasing the momentum of its Instruction Set Architecture (ISA), the industry’s first open, free architecture. RISC-V founding member, SiFive, will host a session detailing the industry’s first open-source RISC-V system-on-chip (SoC). Representatives from UC San Diego, Cornell and the University of Michigan will speak about Celerity, an open source RISC-V SoC with a neural network accelerator fabric. Speaking sessions include:
 

To learn more about the RISC-V Foundation, its open architecture and membership information, please visit: https://riscv.org.

About RISC-V Foundation

RISC-V (pronounced “risk-five”) is a new instruction set architecture (ISA) that was originally designed to support computer architecture research and education and is now set to become a standard open architecture for industry implementations under the governance of the RISC-V Foundation. The RISC-V ISA was originally developed in the Computer Science Division of the EECS Department at the University of California, Berkeley.

The RISC-V Foundation, a non-profit corporation controlled by its members, directs the future development and drives the adoption of the RISC-V ISA. Members of the RISC-V Foundation have access to and participate in the development of the RISC-V ISA specifications and related HW / SW ecosystem.



Contact:

Racepoint Global for RISC-V Foundation
Allison DeLeo, +1 415-694-6700
Email Contact