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Averant's Solidify 6.5 Significantly Improves Combinational and Sequential Equivalency Checking and Clock Domain Crossing Checks

Oakland, Calif. – December 12, 2017 – Averant Inc., the First In Formal™ leader in property verification of RTL designs for digital circuits, today announced the release of Solidify 6.5. Some of the highlights of this release are listed below.

Release 6.5 also contains improvement in property verification, coverage, debugging, GUI, PSL and SVA support. 

"Release 6.5 was the result of close collaboration with our customers and made immediate impact on their verification challenges" commented Ramin Hojati, president of Averant. "This all happened while ideas from the rest of computer science were implemented in Solidify, enriching our development team and customers' experiences". 

Availability 

Release 6.5 is available for use immediately.

About Averant

Averant Inc. is a privately held EDA firm specializing in formal verification of digital designs. Averant’s signature product is Solidify, a robust platform for property, protocol, and automatic design checks – all without the need for simulators or test vectors. Averant's tools are easily adopted into the design flow, and help improve quality, reduce risk, and speed the design process. For more information, visit  http://www.averant.com.



Contact:

Ramin Hojati
Averant, Inc.

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