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Aldec @ DAC 2018: Presenting Innovative SoC Design & Verification Methodologies

HENDERSON, Nev. — (BUSINESS WIRE) — June 20, 2018 — Aldec, Inc., a pioneer in mixed HDL language simulation and hardware-assisted verification solutions for ASIC and FPGA designs, once again innovates and delivers free technical sessions at the Design Automation Conference (DAC) in San Francisco, California.

“This is our 34th year at DAC, and we are excited to present our latest breakthrough innovations in SoC Design and Verification at DAC,” said Louie De Luna, Aldec Director of Marketing. “Together with our product and technology experts, we will cover verification methodologies in the areas of Emulation and Prototyping, Mixed-Signal Simulation, Machine Learning and High-Performance Computing, Static Design Verification, VHDL 2018, Embedded Vision for Automotive, and Safety-Critical Verification Best Practices.”

Technical Sessions and Demos

June 25-27, 2018, from 10:00 a.m. to 6:00 p.m. @ Booth #2628

Register Now – 5 Main Tracks with 18 Technical Presentations

Presentation Track 01: Single Platform for ASIC/SoC Emulation and Prototyping

Presentation Track 02: Mixed-Signal and Mixed-Language Simulation Solutions

Presentation Track 03: Static Design Verification Methodologies

Presentation Track 04: Machine Learning, High Performance Computing and Embedded Vision

Presentation Track 05: Traceability and Reusability for Safety Critical Projects

About Aldec

Established in 1984, Aldec is an industry leader in Electronic Design Verification and offers a patented technology suite including: RTL Design, RTL Simulators, Hardware-Assisted Verification, SoC and ASIC Prototyping, Design Rule Checking, CDC Verification, IP Cores, High-Performance Computing Platforms, Embedded Development Systems, Requirements Lifecycle Management, DO-254 Functional Verification and Military/Aerospace solutions.  www.aldec.com



Contact:

Aldec
Richard Warrilow, +44 (0)1522 789000
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