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Synopsys Extends Leadership with Enhanced Verification Continuum Platform

New Native Tool Integrations Enable up to 5X Higher Verification Performance

MOUNTAIN VIEW, Calif., May 30, 2019 — (PRNewswire) —

Highlights:

Synopsys, Inc. (Nasdaq: SNPS) today announced a new release of its Verification Continuum Platform with new native integrations across verification tools, enabling up to 5X higher verification performance. Verification Continuum is built from the industry's fastest engines developed by Synopsys, including Virtualizer virtual prototyping, SpyGlass® static and VC Formal® verification technologies, VCS® simulation, ZeBu® emulation, Synopsys HAPS® prototyping, Verdi® debug, and VC Verification IP (VIP). Increasing system-on-chip (SoC) complexity, growing SoC software content, and rising time-to-market pressures are driving the need for a highly-efficient verification platform. New enhanced native integrations in Verification Continuum enable performance gains between all verification engines, accelerating time-to-market for complex SoC designs.

"Innovium's highly innovative and production-ready TERALYNX data center Ethernet switch silicon delivers speeds of 2 Terabits-per-second to 12.8 Terabits-per-second," said Avinash Mani, vice president of engineering at Innovium. "To meet our aggressive targets, we took advantage of the industry-leading performance of Synopsys' VCS working together with its VC Verification IP for Ethernet and source code test suites to accelerate the tapeout schedule of our market-leading switch products."

"To gain a competitive edge, we needed a comprehensive solution to improve our verification flow and reduce time-to-market for our high-performance AI solutions," said Bin Liang, vice president at Iluvatar. "Synopsys' VC Formal control and datapath applications, combined with native compile in VCS and unified debug in Verdi, enabled us to uncover dead code in minutes and prove a complex 128 x 128 MAC in one day."

New Native Integrations

"Synopsys' Verification Continuum Platform, built on industry-leading hardware and software verification tools, delivers new native integrations to enable designers to accelerate verification closure," said Ajay Singh, senior vice president, engineering of the Verification Group at Synopsys. "The significant verification R&D investments Synopsys has made since introducing the platform demonstrate our commitment to helping customers reduce time-to-market by months for advanced SoC designs."

Availability

Availability is scheduled for June 2019.

Additional Resources

For more information on Verification Continuum Platform please visit: https://www.synopsys.com/verification.html

About Synopsys

Synopsys, Inc. (Nasdaq: SNPS) is the Silicon to Software partner for innovative companies developing the electronic products and software applications we rely on every day. As the world's 15th largest software company, Synopsys has a long history of being a global leader in electronic design automation (EDA) and semiconductor IP and is also growing its leadership in software security and quality solutions. Whether you're a system-on-chip (SoC) designer creating advanced semiconductors, or a software developer writing applications that require the highest security and quality, Synopsys has the solutions needed to deliver innovative, high-quality, secure products. Learn more at www.synopsys.com.

Editorial Contact:
James Watts 
Synopsys, Inc. 
650-584-1625 
jwatts@synopsys.com  

 

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SOURCE Synopsys, Inc.

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Company Name: Synopsys, Inc.
Web: http://www.synopsys.com
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