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Concept Engineering Accelerates Semiconductor Development With Improved Customizable Debugging Platform

Freiburg, Germany – May 31, 2019 – Concept Engineering, the leader in visualization and debugging technology for electronic circuits and systems, will unveil version 6.11 of the de facto industry standard Vision debugging platform at the Design Automation Conference (DAC), being held June 3 - 6, 2019 at the Las Vegas Convention Center, Las Vegas, NV.

Concept Engineering's Vision debugging platform consists of the following individual tools:

The Vision tools provide powerful debugging and advanced flow automation capabilities for the design of complex SoCs, ASICs, and mixed-signal chips.

New Vision Debugging Platform features are:

“We are dedicated to continue to offer our customers significant performance improvements year after year,” said Gerhard Angst, president and CEO of Concept Engineering.  “With version 6.11, our customers will benefit from improved GUI for smoother and more efficient design exploration and debug. Along with multiple improvements to support development of complex mixed language SoCs.”

The company's updated Vision platform, along with its visualization engines and libraries for EDA tool developers (NIview, T-engine and S-engine), will be demonstrated in the Concept Engineering booth #532 at DAC 2019.

Availability

Version 6.11 Vision tools can be downloaded after DAC 2019 from the company's website www.concept.de.

About Concept Engineering

Concept Engineering is a privately-held company based in Freiburg, Germany, that provides visualization and debugging technology for electronic circuits and systems, including automatic schematic generation technology for all major design levels. The company's technology helps electronic design engineers to easily understand, debug, optimize and document electronic designs. Concept Engineering's software technology is used in many fields in the EDA market, including: RTL development, IP reuse, ASIC and SoC design, FPGA design, analog/mixed-signal design, logic synthesis, design verification, test automation, post-layout analysis, debugging and visualization at system-, RTL-, netlist- and transistor-level.

Editorial Contact:

Michelle Clancy,  Cayenne Communication, Email Contact

+1 503-702-4732



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