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Maxim's Analog PAM4 Chipset Delivers DSP-Level Performance Without Cost, Power and Latency Barriers

SAN JOSE, Calif., March 5, 2020 — (PRNewswire) —  Manufacturers of advanced modules for hyperscale data center applications can reduce power, latency and cost with the industry's first analog PAM4 chipset to target full standards-based performance. PAM4 is a technically challenging coding scheme, especially for optical transmissions, caused by dramatic reduction in signal strength and new requirements for linearity. Technology demonstrations have been shared for many years; however, to date, real-world deployment has been negligible. While engineers are working towards implementing PAM4 using expensive 7nm DSP solutions, the 100G CWDM4 modules continue to be shipped in large volumes at a highly optimized price point. Given this backdrop, large-scale deployment of PAM4 modules will be gated by a few key considerations.

Can PAM4 technology deliver bandwidth at a lower cost and lower power than 100G CWDM4? Can it be produced in high volume with robust system performance?

Maxim's 40G and 100G solutions have led the industry for many years. The 100G ramp was enabled by the introduction of a packaged 25Gbps quad laser driver and CDR that is surface-mounted on the PCB rather than mounted as a die inside the transmit optical sub-assembly. This technically challenging breakthrough has enabled high-volume production of 100G CWDM4. Around 10 million modules are now deployed in data centers around the world using this product. Now, Maxim has taken up the task of solving difficult analog challenges in order to also enable standards-based PAM4 modules with the lowest bill of materials (BOM).

The first products in Maxim's PAM4 family target the 2km FR market and cover both IEEE and Open Eye applications. The transmitter IC includes four channels of electrical input equalizer, PAM4 clock and data recovery (CDR) and integrated externally modulated laser (EML) driver. The matching quad receiver includes integrated transimpedance amplifier (TIA), PAM4 CDR and electrical output driver.

Avoiding the 7nm development costs of DSP removes the BOM cost barrier. Using a traditional transmitter and receiver architecture enables a quick ramp to volume using simple manufacturing techniques. The power consumption for a 200G module using the Maxim chipset is similar to that of a 100G CWDM4 module. Therefore, the cost, power and manufacturability barriers to adoption of PAM4 are resolved. However, this is only meaningful if the solution has robust technical performance. What does that mean? Showing post forward error correction (FEC) error-free operation with a fixed optical input, fixed temperature and days of lab adjustment may make for a good demo, but it does not prove that the technology is robust. Maxim has utilized a highly optimized signal chain and implemented advanced internal control loops to enable the Maxim receiver to match DSP-based receiver performance. It can operate with the lowest pre-FEC BER over the full range of optical input signals from either the matching transmitter or from DSP-based modules. A bonus of using an analog solution is that latency is reduced from hundreds of nanoseconds down to hundreds of picoseconds, which can be critical in some data center applications.

Maxim's PAM4 chipset paves the road to $1/Gbps (200G QSFP56 2km FR), which is key to enabling adoption of 200G CWDM4 over 100G CWDM4. To recap, here are other key advantages of the chipset:

Interested in getting more involved in this advanced PAM4 technology? Maxim is hiring technical experts for our optical team. Learn more at our Optical Career Opportunites page.

 

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SOURCE Maxim Integrated Products, Inc.

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