UVM Simulation-based environment for Ibex RISC-V CPU core with Google RISC-V DV

Presenter: Sunil Sahoo, Product Manager at Aldec
Thursday, September 10, 2020

Abstract:

This presentation showcases the RTL simulation of the SV/UVM testbench of the Ibex core, a 2-stage in-order 32b RISC-V processor core, that is designed to be small and efficient. This SV/UVM testbench uses the open source RISCV-DV random instruction generator, which generates compiled instruction binaries. These binaries are loaded into a simple memory model which then stimulates the Ibex core in Riviera-PRO to run this program in that memory. The ibex core simulation trace log is compared against a golden model generated by an Instruction Set Simulator (ISS) trace log to check for correctness of execution. 

The testbench is created based on its usage of the RISCV-DV random instruction generator developed by Google. There are two memory interface agents that are instantiated within the testbench, one for the instruction fetch interface, and the second for the Load-Store Unit (LSU) interface. These agents which run the slave sequences wait for memory requests from the core, and then grant the requests for instructions and data. There is also an Interrupt Interface Agent which is used to drive stimulus onto the Ibex core’s interrupt pins randomly during test execution. The testbench instantiates a single instance of the memory model that it loads the compiled assembly test program into at the beginning of each test. This serves as a unified instruction/data memory that processes all requests from both of the memory interface agents. The tests located in the Tests and Sequence Library are the main sources of external stimulus generation and checking for this testbench, as the memory interface slave sequences simply serve the core’s memory requests.The tests are all extended from core_ibex_base_test, and manage the entire flow for a single test, from loading the compiled assembly binary program into the testbench memory model, to checking the Ibex core status while the test is running and handling test timeouts. The sequences here are used to drive interrupt and debug stimulus into the core.

The goal of this testbench is to fully verify the Ibex core with 100% coverage. Riviera-PRO can be used to examine the coverage results, visualize the UVM environment and aid in the debug of the verification environment.

Agenda: 

• Introduction to RISCV ibex core
• Review of Testbench Architecture
• Discuss the tests and test plan 
• Review of the RTL/ISS co-simulation flow
• Demo
• Conclusion
• Q&A

Bio:

Sunil Sahoo provides support for customers exploring simulation tools as an Aldec Applications Engineer. His practical engineering experience includes areas in, Digital Designing, Functional Verification and Wireless Communications. He has worked in wide range of engineering positions that include Digital Design Engineer Verification Engineer and  Applications Engineer. He received his B.S. in Electronics and Communications Engineering from VIT University, India in 2008 and M.S in Computer Engineering from Villanova University, PA in 2010.

Aldec is a global industry leader in Electronic Design Verification and offers a patented technology suite including: RTL Design, RTL Simulators, Hardware-Assisted Verification, Embedded, SoC and ASIC Prototyping, Design Rule Checking, CDC Verification, IP Cores, DO-254 Functional Verification and Military/Aerospace solutions.

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