ELK GROVE, Calif., Dec. 16, 2020 (GLOBE NEWSWIRE) -- Accellera Systems Initiative (Accellera), the electronics industry organization focused on the creation and adoption of electronic design automation (EDA) and intellectual property (IP) standards, announced today that the Accellera Universal Verification Methodology (UVM) Working Group has completed work on its UVM-2020 1.0 reference implementation. The new reference implementation is aligned with the latest IEEE 1800.2-2020 Standard for UVM. The IEEE standard is now available for download at no charge under the Accellera-sponsored IEEE Get Program.

"Our UVM Working Group has been very focused on aligning its UVM-2020 1.0 reference implementation with IEEE 1800.2-2020, giving users access to the latest enhancements in compliance with the new standard,” stated Lu Dai, Accellera Chair. “The design and verification community around the globe benefits from our close partnership with the IEEE Standards Association. We continue to leverage our relationship to advance verification productivity and to provide much-needed standards at no cost to the community.”

“The changes in the 2020 LRM are primarily fixes to a small number of API that were erroneously specified in the earlier version in 2017,” stated Mark Strickland, UVM Working Group Chair.  “Along with implementing these LRM updates, the new reference implementation addresses some errata that have existed in the UVM-1.2 implementation.  I’d like to thank the working group for all of their hard work getting the latest reference implementation completed and into the hands of the thousands of engineers in our UVM community.”

The new library implementation provides the latest UVM standard API along with some additional debug API that provides a more cohesive package with the 1800.2-2020 API.  The errata fixes better align the implementation behavior with the LRM documentation.  More detail on the additions and fixes can be found in the documentation provided with the release.

The UVM-2020 1.0 reference implementation can be downloaded for free from Accellera. The IEEE 1 8 00.2-2020 standard is available free of charge from the  IEEE Get program, courtesy of Accellera. Visit the  UVM forum to provide feedback, ask questions, and engage in discussions. For more information on UVM, visit the UVM community page.

Accellera-Sponsored IEEE Get Program
Since its inception in 2010, the Accellera-sponsored IEEE Get Program has resulted in more than 118,000 downloads, providing pre-paid access of electronic design and verification standards to engineers and chip designers worldwide.

About UVM
In development for more than 11 years, UVM has achieved industry-wide success as the standard used by verification engineers to verify complex designs. As an important companion to SystemVerilog, it improves interoperability and reduces the cost of IP development and reuse for each new electronics project. UVM has a very active worldwide  user community and forum and its LinkedIn group has more than 9,200 members.

About Accellera
Accellera Systems Initiative is an independent, not-for profit organization dedicated to create, support, promote and advance system-level design, modeling and verification standards for use by the worldwide electronics industry. The organization accelerates standards development and, as part of its ongoing partnership with the IEEE, its standards are contributed to the IEEE Standards Association for formal standardization and ongoing change control. For more information, please visit www.accellera.org. Find out more about membership. Follow @accellera on Twitter or to comment, please use #accellera. Accellera Global Sponsors are: Cadence; Mentor, A Siemens Business; and Synopsys.

Accellera and Accellera Systems Initiative are trademarks of Accellera Systems Initiative Inc. All other trademarks and trade names are the property of their respective owners.

For more information, contact:
Barbara Benjamin
Public Relations for Accellera Systems Initiative
Phone: +1 503 209 2323
Email: barbara@hipcom.com