At this year’s International Test Conference (10-15 October 2021), Siemens Digital Industries Software is showcasing Integrated Circuit (IC) test and lifecycle management technologies that address the key scaling challenges facing the semiconductor industry now and in the future.
In addition to unveiling new technologies that accelerate test and enable rapid ramping of new process technologies and product qualification, at this year’s ITC event Siemens will also reveal how its customers are adopting packetized test strategies to address the design and system-scaling challenges posed by today’s highly complex systems-on-chip (SoC) designs and prepare for adoption of advanced 2.5D/3D packaging technologies.
Siemens is also celebrating a significant DFT milestone at next week’s show – just one year after introducing the Tessent™ Streaming Scan Network (SSN) design-for-test (DFT) solution, this technology is now deployed and in use with customers worldwide, including all of Siemens’ top five Tessent customers. The conference program at ITC 2021 and Siemens’ virtual booth will feature presentations from multiple customers describing their experience in using SSN technology.
“Last year, Siemens precipitated the industry’s move from traditional DFT architectures to packetized test, with the introduction of Tessent SSN the first commercial, full-flow implementation of packetized scan test DFT technology,” said Geir Eide, director, product management for Tessent DFT products at Siemens Digital Industries Software. “Packetized test architectures form the foundation for effective, productive 3D IC test, along with industry standards such as IEEE 1838. Packetized test is also ideal for very large designs like those associated with semiconductors targeting artificial intelligence (AI) and other fast-growing applications. These capabilities helped spark rapid customer adoption of our ground-breaking Tessent SSN software, which today powers DFT for many of the world’s top IC design companies.”
In addition to the focus on packetized test, Siemens will showcase three new DFT technologies at ITC – Reversible Scan Chain Diagnosis (RVS), Tessent SiliconInsight HP and ATPG Boost – all designed to help manufacturers address timely semiconductor supply chain issues and other emerging challenges:
| • | Designed primarily for use in node qualification and early technology ramp, RVS is proven in use to deliver 4x acceleration in the time required to diagnose faults – a task which, using traditional approaches, can stretch to days or even weeks in the early deployment of a new process. |
| • | SiliconInsight HP targets new product qualification, helping customers reduce time-consuming and costly characterization iterations during first silicon bring-up of new products. It improves ATPG performance of Siemens’ SiliconInsight Desktop by up to 30 percent, increases pin count by more than 2x to 330, and supports packetized implementations via SSN. |
| • | Siemens continues to lead the way in automatic test pattern generation (ATPG) with the debut at ITC 2021 of ATPG Boost – the latest addition to the popular Tessent™ TestKompress™ software. ATPG Boost is designed to enhance IC test coverage and throughput in both hierarchical DFT approaches such as SSN, and traditional, flat designs. Early adopters of ATPG Boost technology are scheduled to share their experiences with ATPG Boost at the ITC Diamond Sponsorship Event (Tuesday, October 12 at 11:00 am PDT) and in the Siemens virtual exhibit booth theater throughout the virtual event. |
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