December 6-8, 2021, Moscone Convention Center, West Hall, Booth #1351
Who
True Circuits, Inc. (TCI), a leading provider of analog and mixed-signal intellectual property (IP) for the semiconductor, systems and electronics industries.
What
At the Design Automation Conference (DAC), TCI will introduce new synthesizable PLLs and DLLs that will continue to raise the bar for timing IP features, performance and flexibility for a wide range of customer applications. For over 23 years, TCI has led the industry with the regular introduction of new timing architectures and IP design types that have defined the timing IP category, and offered chip designers a wide variety of solutions to their timing needs. TCI is proud to introduce our latest timing IP, the synthesizable Precision PLL, micro PLL and micro DLL. Each is available in the latest process nodes and back to 28nm.
The synthesizable Precision PLL generates multiple precision clocks supporting any modulation scheme from almost DC to 10GHz. The outputs can be independently dynamically programmed cycle-by-cycle to any clock period and the clock frequency can be a precise ratio of floating point numbers times the reference frequency. The integrated phase noise is better than 500ps RMS. It is ideal for SerDes, processor and DVFS applications.
The synthesizable micro PLL is a small synthesizable general-purpose PLL that multiplies the reference clock by any integer or fractional-N value from 1 to 500K. It supports reference clock frequencies as low as 32KHz and output frequencies as high as 3GHz. It can stay locked to the reference clock while it changes over a 10:1 frequency range. Because it is synthesizable, it can support spreading as well as other modulation profiles. It is relatively low power, very fast locking and can quickly restart from a sleep mode.
The synthesizable micro DLL is a small synthesizable DLL with a master and multiple slaves topology. It can support reference frequencies typically in the range of 500MHz to 3GHz and track reference changes over an 8:1 frequency range while providing 9-bit accuracy in slave delay programming. Slave delays can be changed glitch free and the DLL can quickly restart from a sleep mode. It has a very small zero code offset that can be precisely cancelled.
TCI will also showcase its high performance, silicon proven DDR PHY with fully automatic training managed by a light weight special purpose processor, and remarkable physical flexibility to adapt to each customer’s die floorplan and package. The DDR PHY has been developed using the powerful custom design automation tools that have made TCI’s line of high performance PLLs and DLLs a staple in the semiconductor industry for over 23 years. The PHY supports LPDDR5, DDR4, LPDDR4, DDR3, and LPDDR3 protocols. The availability of this silicon proven PHY means customers can now license a PHY with significant performance and features without all the implementation and timing closure hassles that are common with current DDR offerings.
The DDR PHY supports up to LPDDR5, and has undergone extensive silicon testing in our lab and has achieved DDR4 3200Mbps and DDR3 2133Mbps in TSMC 28nm HPC+ across PVT without bit errors. TCI went to great lengths to implement the DDR 4/3 PHY test chip just as our customers would implement a product chip. We used industry standard tools to synthesize, place and route the test chip, incorporated a Northwest Logic controller and Aragio Solutions DDR and General Purpose IOs, utilized custom high quality test boards and sockets, and used Micron memories. Taking this approach allowed us to experience and evaluate every aspect of the implementation of the PHY so we can better support our customers.
During the show, we will be giving short presentations and demos of the PHY in action. This will be a great opportunity to ask questions and learn what makes a TCI DDR PHY hard macro one special piece of IP.
We will also feature our complete line of standardized and silicon-proven general purpose, clock generator, deskew, spread spectrum, Ultra and IoT PLLs, and multi-slave and multi-phase DLLs that spans nearly all performance points, features and foundry processes typically requested by ASIC, FPGA and SoC designers. These high quality, low-jitter PLL and DLL hard macros are suited to a wide variety of interface standards and chip applications. They are pin-programmable, highly process tolerant, reusable and available for delivery in TSMC, GLOBALFOUNDRIES and UMC processes from 180nm to 4nm.
As always, we are glad to discuss your IP needs, including IP selection, IP integration, IP reuse, jitter specifications and silicon testing, so please stop by our booth #1351 and spend some time with the timing experts!
When and Where
Moscone Convention Center, West Hall, San Francisco, CA
True Circuits Booth #1351
Monday - Wednesday, December 6-8, 10:00 AM to 6:00 PM
Contacts
For more information about True Circuits' PLLs, DLLs and DDR PHYs, please visit
www.truecircuits.com.
For more information about the Design Automation Conference, please visit www.dac.com.
About True Circuits Standard PLLs and DLLs
True Circuits offers a complete family of standardized and silicon-proven general purpose, clock generator, deskew, spread spectrum, IoT and Ultra PLLs, and multi-slave and multi-phase DLLs that spans nearly all performance points and features typically requested by ASIC, FPGA and SoC designers. These high quality, low-jitter PLL and DLL hard macros are suited to a wide variety of interface standards and chip applications. They are pin-programmable, highly process tolerant and reusable. They are also easy to integrate and are fully supported, so customers can reduce both design and silicon risks.
True Circuits PLLs support a wide range of frequencies, multiplication factors and functions over which they deliver optimal performance, avoiding the cost and complexity of licensing multiple point-solution PLLs or fiddling with digital PLLs. TCI’s PLLs are available with ring-oscillator and LC-tank architectures, fractional-N division and frequency spreading for EMI reduction. TCI's DLLs are available in multi-slave and multi-phase versions and different sizes and form factors. They delay a set of signals by precise and adjustable fractions of a reference clock cycle independent of voltage and temperature and are ideal for high-speed DDR and ONFI interface applications. Customized PLL and DLL solutions are also available for specialized chip applications.
True Circuits PLLs and DLLs are available for immediate customer delivery in TSMC, GLOBALFOUNDRIES and UMC processes from 180nm to 4nm. For more information about True Circuits IP products, visit www.truecircuits.com/tci_technology.html and www.truecircuits.com/product_matrix.html.
About True Circuits DDR PHYs
The DDR PHY is a high-performance, scalable system using a radically new architecture that continuously and automatically adjusts each pin individually, correcting skew within byte lanes. This state-of-the-art tuning acts independently on each pin, data phase and chip select value. Read gate and data eye timing are also continuously adjusted. Automatic training is included for multi-cycle write leveling and read gate timing, read/write data eye timing, and PHY Vref and DRAM Vref settings.
The PHY employs a localized and optimized PHY-to-memory controller interface to ease timing closure. The circuitry in each pin is able to measure the data eye and jitter, and calculate flight delays. The PHY also includes a full speed read/write BIST, which tests the complete read and write paths of every pin simultaneously with pseudo-random data.
Remarkable physical flexibility allows the PHY to adapt to each customer's die floorplan and package constraints, yet is delivered and verified as a single unit for easy timing closure with no assembly required. The PHY supports LPDDR5, DDR4, LPDDR4, DDR3 and LPDDR3, and is DFI 5.1 compliant. When combined with an appropriate DDR memory controller, a complete and fully-automatic DDR system is realized.
The True Circuits DDR PHY is silicon proven and immediately available for customer delivery in TSMC's 28/22nm HPC/HPC+ processes. The PHY will be available in additional TSMC and GLOBALFOUNDRIES processes in the very near future. Interested customers can obtain more product information on the web at http://www.truecircuits.com/ddr_phy.html or by contacting True Circuits at sales@truecircuits.com.
About True Circuits
True Circuits develops and markets a broad range of industry leading PLLs, DLLs and DDR PHY hard macros for ICs for the semiconductor, systems and electronics industries. TCI's robust state-of-the-art circuits, methodical and proven design strategy, and close association with the world's leading foundries, IDMs, and design services companies allow the company to quickly and reliably create new and innovative designs in a variety of advanced process technologies. Over the last 23 years, True Circuits has distinguished itself as the technology leader in the timing IP space, and its PLLs and DLLs are used extensively around the world in its customers' products with production volumes well into the billions.
True Circuits is headquartered at 4300 El Camino Real, Suite 200, Los Altos, California 94022 and can be found on the web at www.truecircuits.com. Product inquiries can be made by calling the company directly at (650) 949-3400 or via e-mail at Email Contact.
Press Contact: Kimberly Toan, True Circuits, Inc., (650) 949-3400, Ext. 3404, Email Contact.
Acronyms and definitions:
ASIC Application Specific IC
IoT Internet of Things
DLL Delay-Locked Loop
IP Intellectual Property
DDR Double Data Rate
ONFI Open NAND Flash Interface
FPGA Field Programmable Gate Array
PLL Phase-Locked Loop
IC Integrated Circuit
SoC System on a Chip
The Precision PLL is a trademark of True Circuits, Inc.
The Micro PLL is a trademark of True Circuits, Inc.
The Micro DLL is a trademark of True Circuits, Inc.
The IoT PLL is a trademark of True Circuits, Inc.
The Ultra PLL is a trademark of True Circuits, Inc.
The True Circuits logo is a trademark of True Circuits, Inc.
All other trademarks and tradenames are the property of their respective owners.