Monheim am Rhein, Germany – October 10th, 2022

SEGGER, a leading supplier of software libraries, development tools, debug probes and flash programmers, today announced native J-Link debug probe support for select instances of the Cadence Tensilica Processor IP, a portfolio of configurable and extensible controllers and DSPs.

The Cadence Tensilica cores supported in the first implementation phase are the Tensilica Xtensa LX7 CPU, a number of Tensilica HiFi DSPs (HiFi 4, HiFi 3z, HiFi 3, and HiFi 1), and also the Tensilica Fusion F1 DSP. The latest hardware versions of all commercial SEGGER J-Link models ( J-Link BASE, J-Link PLUS, J-Link ULTRA+ , and J-Link PRO ) now support high-speed download and debugging of these cores via JTAG and SWD.