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Astera Labs’ PCIe and CXL Connectivity Solutions Complete Interoperability Validation with 5th Gen Intel Xeon Scalable Processors

Leo CXL Smart Memory Controllers and Aries PCIe/CXL Smart DSP Retimers Validated for Robust Interoperation in Astera Labs’ Cloud-Scale Interop Lab

SANTA CLARA, Calif. — (BUSINESS WIRE) — December 14, 2023 — Astera Labs, the global leader in semiconductor-based connectivity solutions for cloud and AI infrastructure, today announced its collaboration with Intel to offer its portfolio of PCIe® and CXL® solutions to unleash the full potential of 5th Gen Intel Xeon Scalable processors. Astera Labs has completed rigorous interoperability testing in its Cloud-Scale Interop Lab to enable hyperscalers and OEMs to mitigate design risks, accelerate time-to-market, and deploy Intel-based platforms with confidence at cloud-scale.

Today's workloads demand increased compute and memory bandwidth. 5th Gen Intel Xeon Scalable processors with increased cores and built-in accelerators deliver additional memory bandwidth and capacity. Astera Labs' Leo CXL Smart Memory Controllers build on this, increasing the available memory capability. Leo supports fine-grained heterogeneous interleaving of native CPU, DRAM, and CXL-attached memory and shows significant performance benefits for memory-intensive applications. Leo has undergone intensive feature validation, thorough interop testing, and rigorous application-level testing by Astera Labs to enable cloud-scale deployment.

Astera Labs’ Aries PCIe/CXL Smart DSP Retimers are already the most widely deployed retimers for cloud and AI infrastructure today. As server density increases and larger disaggregated architectures are deployed, connectivity between processors, accelerators, network interface cards, switches and other PCIe 5.0 or CXL devices becomes more challenging. Aries extends PCIe 5.0 reach by 3x, allowing compute and AI clusters to be deployed for Generative AI training workloads. Purpose-built for cloud and AI, Aries also includes a low latency mode to ensure CXL solutions such as Leo deliver the best performance for latency-sensitive applications.

In its Cloud-Scale Interop Lab, Astera Labs rigorously tests its portfolio for standards compliance and system-level interoperation with all major hosts, endpoints, and memory modules. This testing enables plug-and-play interoperability for deploying cloud and AI infrastructure at scale. Customers can request Interop Reports with detailed testing results at www.asteralabs.com/GetReports.

Sanjay Gajendra, President and Chief Operating Officer, Astera Labs, said, “We value our strategic collaboration with Intel as we work together to deliver performant and reliable PCIe and CXL solutions for our mutual customers and we continue to innovate and meet the needs of future data centers. Our Leo memory controllers and Aries retimers, combined with 5th Gen Intel Xeon Scalable Processors, deliver the right recipe for unprecedented scale in modern day data centers.”

Lisa Spelman, CVP, Xeon Products & Solutions, Intel, said, “With support for CXL, 5th Gen Intel Xeon Scalable processors deliver enhanced performance for memory intensive workloads. The addition of a technology like Astera Labs’ Leo CXL Smart Memory Controller enables system configurations right-sized to meet customer demand. We look forward to continued collaboration to bring CXL based memory solutions to market.”

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About Astera Labs

Our PCIe, CXL and Ethernet semiconductor-based connectivity solutions are purpose-built to unleash the full potential of cloud and AI infrastructure. Inspired by trusted partnerships with hyperscalers and the data center ecosystem, we are an innovation leader of products that are customizable, interoperable, and reliable. Discover how we are transforming modern data-driven applications at www.asteralabs.com.

© Astera Labs, Inc. Astera Labs, and its stylized logo, are trademarks of Astera Labs, Inc. or its affiliates. Other names and brands may be claimed as the property of others.

Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries.


Contact:

Lori Zielinski
lori.zielinski@asteralabs.com