Figure 5

In Figure 5, by default, G3 of blk1 directly master to Gi, however if there is a timing exception specified from Gi to elsewhere, it has a potential to leak out of blk0 and affect FF cluster of flops. To prevent such a situation, the tool creates a generated clock (Gb) at the boundary of the blk0.  Thus, the promoted SDC will contain C1, G2, Gi, Gb and G3 clocks.

Satisfying different Methodologies

As the chip undergoes different stages of implementation, different types of SDC’s are required. For example, for logic synthesis the SDC that propagates the fastest clock is sufficient. However, for P&R or for final signoff an SDC with all clock propagating is required. To satisfy this situation, the tool provides additional configurability. The main ones are:

1. Single Block Level Clock to Single Top-Level Clock (SBST)
2. Multiple Block Level Clocks to Multiple Top-Level Clocks (MBMT)

In the SBST method, the clocks are mapped from a single clock to a single clock. Thus, if there are multiple clocks at the top level, but a single clock at the block level, the tool maps the single block level clock to the fastest top-level clock.

Figure 6

In figure 6, the original block level clock is B1 and Gi, whereas the top-level clocks are C1 and C2. During the SBST promotion flow, the B1 was replaced by G1, however, G1 now masters to the C1 clock, since C1 is faster than C2. C2 propagates up to the BLOCK but is blocked at the boundary.

For STA signoff, propagation of all clocks may be required in order to time all the paths related to them. For such a case, the MBMT type of promotion is used to generate such timing constraints. In a strict sense, this method is not a pure constraints promotion, rather it’s a promotion combined with completion, so that it can satisfy the implementation and sign off requirements.

Figure 7

In the MBMT method, additional clocks are created throughout the chain of propagation of original block clocks in order to propagate the additional top clocks. Figure 7 illustrates this behavior. The C1 clock domain promotion is identical to the SBST method, however, for the C2 clock domain, the G2 clock is created which now masters to C2 along with G3 clock that masters to G2.

Conclusion

Excellicon’s Constraints Manager is highly configurable and very flexible in terms of usage. It allows users to provide whatever is available. For example, in the early stages of the chip design, the timing constraints may be available only for some IP blocks, but not for other blocks. In this case, the Constraints Manager will extract the timing information for the blocks without the SDC and promote the ones with the SDC to the Top level.

In other cases, particularly for the next revisions of the chip, the timing constraints for most blocks are available along with somewhat mature top-level constraints. In this case, the tool promotes and “stitches” the constraints together and the extraction only takes place for the logic that is not clocked. The mix and match approach satisfies all aspects of chip development stages and all layers of hierarchies.

Excellicon’s automated solution has been used for various types of chips in various industries with necessary flexibility to be adopted to desired methodology. The configurability provided by Excellicon tools ensures that the users have the most flexibility and control over the tool behavior and output to fit their specific needs.

In conclusion, Excellicon’s fully automated and patented flow can promote the timing information to the higher levels of hierarchy in minutes. This 1) ensures completeness and 100% coverage of timing constraints at the top level, and 2) Simplifies equivalency checks when comparing various layers of hierarchy against lower levels or integrated blocks.

Author: Himanshu Bhatnagar

About Excellicon

Excellicon is an innovative provider of end-to-end Timing Constraints Analysis and Early design planning and debugging solutions for the automation of constraints, authoring, completion, and validation from RTL to GDS with innovative analysis and debugging infrastructures. Excellicon products are also targeting early design planning and viability analysis helping to detect design implementation issues very early on. Excellicon products are Constraints Manager (ConMan), Constraints Certifier (ConCert), Exception-ToolBox (ET), Budgeting-Tool Box (BT), Equivalence-Checker (EQ), ConStruct, ConTree, and ConTour address the needs of designers at every stage of SOC design and implementation in a unified environment. – Design & Timing Closure; Done Once! Done Right!

For further information contact:

Rick Eram

www.excellicon.com