Verification Now 2008 Overview
Complex system-on-chip (SoC) designs require a well-thought-out verification strategy. Proper verification planning and the use of advanced techniques in a SystemVerilog environment can help guarantee that the design and testbench verification process will be successful and efficient. The full-day technical seminar will provide design and verification engineers with information on why verification planning is needed, and how to effectively apply planning to existing design methodologies. The seminar also will look at the importance of layered stimulus generation techniques to build flexibility and reusability into a SystemVerilog testbench, and will outline how to implement those techniques.
The program will be presented by J.L. Gray of Verilab, author of the Cool Verification blog. The agenda and detailed abstracts on requirements-based verification and on building flexible and reusable testbenches using a layered approach to stimulus generation can be found on the Verification Now website at http://www.verification-now.com. Sponsors of the event are Certess, Inc., Denali Software, Inc., and SpringSoft Inc., and media sponsor is EDN magazine.
Seminars will be held in:
- Santa Clara, Calif., at TechMart on Tuesday, October 14, 2008
- Austin, Tex., at the Hyatt Regency Austin on Tuesday, October 21, 2008
- Yokohama City, Japan, at the Pan Pacific Yokohama Bay Hotel on Monday, October 27, 2008
- Taipei, Taiwan, at the Grand Hyatt Taipei on Friday, October 31, 2008
- Herzliya, Israel, at the Dan Accadia Herzliya Hotel on Monday, November 3, 2008
Register for this free seminar, including breakfast and lunch, at http://www.verification-now.com/register.html.
For additional information, please see the Verification Now 2008 website -- http://www.verification-now.com/ -- or contact us at Email Contact.
About the Sponsors
Certess, Inc.
Certess, Inc., is the only electronic design automation company providing functional qualification products for companies that create and integrate complex design blocks for systems on a chip (SoCs) or intellectual property (IP).The company’s technology provides design and verification engineers with an objective way to evaluate and improve the completeness of the verification environment, resulting in a shorter and more predictable process to integrate SoC designs and ensure high-quality designs. The company is headquartered in Campbell, CA. For additional information, see www.certess.com.
Denali Software
Denali Software, Inc., is a world-leading provider of electronic design automation (EDA) software and semiconductor intellectual property (IP) for system-on-chip (SoC) design and verification. Denali delivers the industry’s most trusted solutions for deploying PCI Express, NAND Flash and DDR DRAM subsystems. Developers use Denali’s EDA, IP and services to reduce risk and speed time-to-market for electronic system and chip design. Denali is headquartered in Sunnyvale, California, and has offices around the world to serve the global electronics industry. More information about Denali, its products and services is available at www.denali.com.
SpringSoft, Inc.
SpringSoft, Inc., (TAIEX: 2473) is a global supplier of specialized automation technologies that accelerate engineers during the design, verification and debug of complex digital, analog and mixed-signal ICs, ASICs, microprocessors, and SoCs. Its award-winning product portfolio features the Novas Verification Enhancement and Laker Custom IC Design solutions used by more than 400 of today's leading IDM and fabless semiconductor companies, foundries, and electronic systems OEMs. Headquartered in Hsinchu, Taiwan, and San Jose, California, SpringSoft is the largest company in Asia specializing in IC design software and a recognized industry leader in customer service, with more than 400 employees located in multiple R&D sites and local support offices around the world. For more information, visit www.springsoft.com.
Verilab, Inc.
Verilab is an elite international team of verification experts specializing in solving the toughest problems in VLSI functional verification. Our consultants have expertise in all major functional verification languages and methodologies, and have completed over 150 in a variety of domains including CPU, networking, SoC, smartcard and automotive applications. Verilab consultants have assisted clients around the world with training, methodology evaluation, project management, and testbench development from our sites in Austin, Munich, Bristol and Glasgow.
Contact:
Cayenne Communication,
Michelle Clancy, +1-252-940-0981
Email Contact