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CoWare Reduces Design Cost for Complex ARM AMBA Platform Optimization

SAN JOSE, Calif. — (BUSINESS WIRE) — June 15, 2009 CoWare®, Inc., the leading supplier of Electronic System Virtualization™ software and services, announced the availability of a new Interconnect and Memory Subsystem Performance Optimization design flow for CoWare Platform Architect, enabling early and efficient optimization of next-generation system-on-chip (SoC) architectures using ARM® AMBA®-based virtual platforms.

CoWare virtual platforms for architecture design are the virtualized representation of an electronic system used for the purpose of system-level performance analysis and architecture optimization. The new flow provides system architects with the ability to efficiently capture the dynamic performance workloads of each application subsystem of a multi-function SoC in the form of transaction traffic, months before software is available and with minimum modeling effort using a well-defined, repeatable methodology.

CoWare is the leading global supplier of electronic system virtualization solutions for software development, platform architecture design and platform verification of ARM-based platforms. CoWare combines ARM instruction-accurate processor models and implementation-accurate Carbonized ARM models within one standards-based SystemC design environment. The CoWare solutions enable engineers to take full advantage of the capabilities of the entire range of ARM system elements in the context of the actual design; from ARM memory controllers and interconnects to application and embedded processors and embedded firmware.

“CoWare has been the leader in electronic system virtualization solutions for ARM technology-based platforms for more than 10 years now,” said Johannes Stahl, vice president of marketing and business development at CoWare. “This new flow captures the production-proven design methods successfully deployed by CoWare customers to analyze and improve next-generation system performance and cost sooner by using transaction traffic generation, while retaining full support in the same environment for the HW-SW performance validation of early architectural decisions using cycle-accurate processor models and software, as they become available throughout the development process.”

CoWare Capabilities Enabling the New Flow

The new Interconnect and Memory Subsystem Performance Optimization design flow for CoWare Platform Architect is enabled by CoWare’s advanced system-level design features, including:

Availability

CoWare Platform Architect tool and IP model enhancements and CoWare CoStart services are available immediately for use with the 2009.1.1 release.

About CoWare

CoWare is the leading global supplier of electronic system virtualization software and services. IP, semiconductor, and electronics companies use CoWare virtualization solutions to design better processor- and software-intensive products faster. CoWare solutions solve the new design challenges associated with platform architecture design, platform verification, application sub-system design, processor design, DSP algorithm design, and software development, and are based on open industry standards including SystemC. These solutions also enable IP and semiconductor companies to implement more effective go-to-market strategies. CoWare’s corporate investors include ARM [(LSE: ARM); (Nasdaq: ARMH)], Cadence Design Systems (NASDAQ: CDNS), STMicroelectronics (NYSE: STM), and Sony Corporation (NYSE: SNE). CoWare is headquartered in San Jose, Calif., and has offices around the world. For more information about CoWare and its products and services visit http://www.coware.com.

CoWare is a registered trademark of CoWare, Inc. All other trademarks are the property of their respective owners. ARM and AMBA are registered trademarks of ARM Limited.



Contact:

CoWare, Inc.
Mindy Palmer, 408-392-8513
Director, Marketing Communications
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