The OSVVM testbench framework looks identical to other frameworks, including SystemVerilog. It includes verification components (AxiStreamTransmitter and AxiStreamReceiver) and TestCtrl (the test sequencer) as shown in Figure 1. The top level of the testbench connects the components together (using the same methods as in RTL design) and is often called a test harness. Connections between the verification components and TestCtrl use VHDL records (which we call the transaction interface).   Connections between the verification components and the DUT are the DUT interfaces (such as AxiStream, UART, AXI4, SPI, and I2C).  

There are three steps required to create an OSVVM verification component:

1. Define the transaction interface (in OSVVM it is a record)
2. Define the transaction procedures (the call API for the test sequencer)
3. Define the internals of the verification component itself.  

OSVVM model independent transactions are one of our latest innovations – added to OSVVM in 2020.07. For a class of interfaces, the model independent transactions define the transaction interface and transaction procedures. OSVVM has defined these for address bus interfaces (such as AXI, Avalon, X86, …) and streaming type interfaces (such as UART, AXI Stream, …).